3-bit asynchronous up/down counter

An asynchronous up/down counter is a ripple counter that can count either upward (0, 1, 2, …, 7) or downward (7, 6, …, 0) depending on a mode control input M. Only the first flip-flop gets the external clock; each later flip-flop is clocked by the previous stage.

Principle

For negative-edge triggered JK flip-flops with $J = K = 1$ (toggle mode):

• Up count: the next flip-flop must toggle when the previous output goes $1 \to 0$, so it is clocked from $Q$.
• Down count: the next flip-flop must toggle when the previous output goes $0 \to 1$, i.e. when $\overline{Q}$ goes $1 \to 0$, so it is clocked from $\overline{Q}$.

A 2-input AND-OR (or MUX) between stages selects $Q$ or $\overline{Q}$:

$$CLK_1 = M\,Q_0 + \overline{M}\,\overline{Q_0}, \qquad CLK_2 = M\,Q_1 + \overline{M}\,\overline{Q_1}$$

M = 1 gives up counting, M = 0 gives down counting.

Circuit

 M=1: UP    M=0: DOWN      (all J = K = 1)

       +-----+  Q0 --[AND]--+
CLK --o| FF0 |       M      +--[OR]--> CLK of FF1
       +-----+ Q0' --[AND]--+
                     M'
       +-----+  Q1 --[AND]--+
 ... -o| FF1 |       M      +--[OR]--> CLK of FF2
       +-----+ Q1' --[AND]--+
                     M'

Outputs $Q_2Q_1Q_0$ (Q0 = LSB) give the count.

Operation

1. M = 1 (up): FF0 toggles on every falling clock edge. When $Q_0$ falls from 1 to 0, FF1 toggles; when $Q_1$ falls, FF2 toggles. Sequence: 000, 001, 010, …, 111, 000.
2. M = 0 (down): FF1 toggles when $Q_0$ rises (its $\overline{Q_0}$ falls), and FF2 toggles when $Q_1$ rises. Sequence: 000, 111, 110, …, 001, 000.

Timing diagram: up mode (M = 1)

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    1   2   3   4   5   6   7   0

Timing diagram: down mode (M = 0)

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q1   ____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    7   6   5   4   3   2   1   0

Points to note

• Each stage waits for the previous one, so the total delay is $3\,t_{pd}$ and short false states appear during transitions.
• The mode M should be changed only when the clock is steady; switching M can create an extra edge at the next stage and give a wrong count.