- 2075 Chaitra · 6 marks
4-bit asynchronous down counter
Short answer
A 4-bit asynchronous down counter uses four negative-edge JK flip-flops (J=K=1), each clocked by Q' of the preceding stage. Starting from 0000, the first pulse toggles all to 1111, then it counts down 15,14,…,0. Q0 divides clock by 2, Q1 by 4, Q2 by 8, and Q3 by 16.
Explain the working principle of 4 bit down asynchronous counter with neat timing diagram using negative clock edge triggering.
A 4-bit asynchronous down counter counts 15, 14, 13, …, 0 and then back to 15, decreasing by one on every clock pulse. Only the first flip-flop gets the external clock.
Principle
In a down count a flip-flop must toggle when the next lower bit changes from 0 to 1 (a "borrow"). With negative-edge triggered flip-flops, a 0→1 change of is a 1→0 change of . So each stage is clocked from the of the previous stage.
Circuit
Four negative-edge JK flip-flops, all with (toggle mode). CLK → FF0; → FF1; → FF2; → FF3. The count is read from .
J=K=1 J=K=1 J=K=1 J=K=1
+-----+ +-----+ +-----+ +-----+
CLK-o FF0 |Q0'-o FF1 |Q1'-o FF2 |Q2'-o FF3 |Q3
+-----+ +-----+ +-----+ +-----+
Working
- Start with 0000. On the first falling edge FF0 toggles: goes 0→1, so falls and FF1 toggles; goes 0→1, so FF2 toggles; and then FF3 toggles. The count becomes 1111 (15).
- Next edge: goes 1→0, rises, so FF1 does not change: 1110 (14).
- Next edge: 0→1 toggles FF1 ( 1→0), which does not clock FF2: 1101 (13).
- The count keeps falling by one per pulse: 12, 11, …, 1, 0, and then 15 again.
| Clock | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
|---|---|---|---|---|---|---|---|---|---|
| Q3Q2Q1Q0 | 0000 | 1111 | 1110 | 1101 | 1100 | 1011 | 1010 | 1001 | 1000 |
| Count | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
and continuing 0111 (7), 0110 (6), …, 0000 (0).
Timing diagram (falling-edge clock)
CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3 ____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q2 ____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
Q1 ____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______
Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt 0 15 14 13 12 11 10 9 8 7 6 5 4
Each changes when the of the stage before it goes high (its falls). In practice each stage adds a delay , so the change from 0000 to 1111 takes . The circuit also divides frequency: , , , .
✓ Answer checked by Claude Opus 5.5 (high effort)
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