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4-bit asynchronous down counter

Short answer

A 4-bit asynchronous down counter uses four negative-edge JK flip-flops (J=K=1), each clocked by Q' of the preceding stage. Starting from 0000, the first pulse toggles all to 1111, then it counts down 15,14,…,0. Q0 divides clock by 2, Q1 by 4, Q2 by 8, and Q3 by 16.

Explain the working principle of 4 bit down asynchronous counter with neat timing diagram using negative clock edge triggering.

A 4-bit asynchronous down counter counts 15, 14, 13, …, 0 and then back to 15, decreasing by one on every clock pulse. Only the first flip-flop gets the external clock.

Principle

In a down count a flip-flop must toggle when the next lower bit changes from 0 to 1 (a "borrow"). With negative-edge triggered flip-flops, a 0→1 change of QQ is a 1→0 change of Q‾\overline{Q}. So each stage is clocked from the Q‾\overline{Q} of the previous stage.

Circuit

Four negative-edge JK flip-flops, all with J=K=1J = K = 1 (toggle mode). CLK → FF0; Q0‾\overline{Q_0} → FF1; Q1‾\overline{Q_1} → FF2; Q2‾\overline{Q_2} → FF3. The count is read from Q3Q2Q1Q0Q_3Q_2Q_1Q_0.

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-o FF0 |Q0'-o FF1 |Q1'-o FF2 |Q2'-o FF3 |Q3
    +-----+     +-----+     +-----+     +-----+

Working

  1. Start with 0000. On the first falling edge FF0 toggles: Q0Q_0 goes 0→1, so Q0‾\overline{Q_0} falls and FF1 toggles; Q1Q_1 goes 0→1, so FF2 toggles; and then FF3 toggles. The count becomes 1111 (15).
  2. Next edge: Q0Q_0 goes 1→0, Q0‾\overline{Q_0} rises, so FF1 does not change: 1110 (14).
  3. Next edge: Q0Q_0 0→1 toggles FF1 (Q1Q_1 1→0), which does not clock FF2: 1101 (13).
  4. The count keeps falling by one per pulse: 12, 11, …, 1, 0, and then 15 again.
Clock012345678
Q3Q2Q1Q0000011111110110111001011101010011000
Count015141312111098

and continuing 0111 (7), 0110 (6), …, 0000 (0).

Timing diagram (falling-edge clock)

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q2   ____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
Q1   ____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    15  14  13  12  11  10  9   8   7   6   5   4

Each QQ changes when the QQ of the stage before it goes high (its Q‾\overline{Q} falls). In practice each stage adds a delay tpdt_{pd}, so the change from 0000 to 1111 takes 4 tpd4\,t_{pd}. The circuit also divides frequency: Q0=f/2Q_0 = f/2, Q1=f/4Q_1 = f/4, Q2=f/8Q_2 = f/8, Q3=f/16Q_3 = f/16.

✓ Answer checked by Claude Opus 5.5 (high effort)

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