Sync vs async; 3-bit synchronous down counter

Synchronous vs asynchronous counter

Design of 3-bit synchronous down counter (JK)

A 3-bit down counter counts 7, 6, 5, …, 0 and then returns to 7. Three JK flip-flops ($Q_2Q_1Q_0$) share one clock.

Excitation table (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)

K-maps

$J_0$ and $K_0$ are 1 in every row (Q0 toggles every clock), so $J_0 = K_0 = 1$. $J_1$ and $K_1$ have the same map, and so do $J_2$ and $K_2$.

Equations

$$\begin{aligned} &J_2 = \overline{Q_1}\overline{Q_0},\quad K_2 = \overline{Q_1}\overline{Q_0} \\ &J_1 = \overline{Q_0},\quad K_1 = \overline{Q_0} \\ &J_0 = 1,\quad K_0 = 1 \end{aligned}$$

In words, a stage toggles when all lower bits are 0 (the "borrow" condition), just as an up counter stage toggles when all lower bits are 1.

Circuit diagram

   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = K0 = 1
J1 = K1 = Q0'
J2 = K2 = Q1'.Q0'   (one 2-input AND gate)

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q1   ____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    7   6   5   4   3   2   1   0

All outputs change together on the falling clock edge, so no ripple delay or false state appears.