Sync vs async; 3-bit Gray code counter

Synchronous over asynchronous counter

Advantages

• All flip-flops change together, so the total delay is one flip-flop delay plus one gate delay; the counter can run at a much higher clock frequency.
• No ripple, so there are no temporary false states and no glitches when outputs are decoded.
• Any count sequence (Gray, BCD, arbitrary) can be designed directly from the state table.
• Maximum frequency does not fall as more stages are added (with parallel carry).

Disadvantages

• Needs extra combinational logic (AND gates) for each stage, so the circuit is more complex and costlier.
• The clock drives every flip-flop, so the clock line has a larger load.
• Design takes more effort (excitation table, K-maps).

Design: 3-bit synchronous Gray code counter (D flip-flops)

Sequence: 000 → 001 → 011 → 010 → 110 → 111 → 101 → 100 → 000. 8 states, so 3 D flip-flops with a common clock. For a D flip-flop, $D = Q^+$, so the next-state columns give the D inputs directly.

K-maps

Equations

$$\begin{aligned} D_2 &= Q_2Q_0 + Q_1\overline{Q_0} \\ D_1 &= \overline{Q_2}Q_0 + Q_1\overline{Q_0} \\ D_0 &= Q_2Q_1 + \overline{Q_2}\overline{Q_1} = \overline{Q_2 \oplus Q_1} \end{aligned}$$

Circuit

   +-----+       +-----+       +-----+
D0>|D   Q|-Q0 D1>|D   Q|-Q1 D2>|D   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
   |     |       |     |       |     |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
D2 = Q2.Q0 + Q1.Q0'
D1 = Q2'.Q0 + Q1.Q0'
D0 = XNOR(Q2, Q1)

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___
Q1   ________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________
Q0   ____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______
Cnt  000  001 011 010 110 111 101 100 000

Only one output changes per clock, as required by the Gray code.