3-bit Gray code synchronous counter

A 3-bit Gray code counter steps through the 3-bit Gray sequence, in which only one bit changes between successive counts: 000 → 001 → 011 → 010 → 110 → 111 → 101 → 100 → 000. A synchronous design with JK flip-flops is given below.

Step 1: Flip-flops

8 states, so 3 JK flip-flops ($Q_2Q_1Q_0$) with a common clock. No unused states.

JK excitation: 0→0: J=0, K=X; 0→1: J=1, K=X; 1→0: J=X, K=1; 1→1: J=X, K=0.

Step 2: Excitation table

Step 3: K-maps

Step 4: Equations

$$\begin{aligned} &J_2 = Q_1\overline{Q_0},\quad K_2 = \overline{Q_1}\overline{Q_0} \\ &J_1 = \overline{Q_2}Q_0,\quad K_1 = Q_2Q_0 \\ &J_0 = Q_2Q_1 + \overline{Q_2}\overline{Q_1},\quad K_0 = Q_2\overline{Q_1} + \overline{Q_2}Q_1 \end{aligned}$$

So $J_0 = \overline{Q_2 \oplus Q_1}$ (XNOR) and $K_0 = Q_2 \oplus Q_1$ (XOR).

Step 5: Circuit diagram

   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = XNOR(Q2,Q1)   K0 = XOR(Q2,Q1)
J1 = Q2'.Q0        K1 = Q2.Q0
J2 = Q1.Q0'        K2 = Q1'.Q0'

Gates needed: one XOR, one XNOR (or XOR + NOT) and four 2-input AND gates.

Step 6: Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___
Q1   ________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________
Q0   ____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______
Cnt  000  001 011 010 110 111 101 100 000

Only one output changes at each clock edge, which is the main advantage of a Gray code counter (no decoding glitches, low noise).