Structural modelling; 3-bit up counter

Structural modelling

In structural modelling a design is described as a set of components connected by signals, like a schematic in text form. Each component is first declared (component ... end component) and then instantiated with a port map that connects its ports to signals or to the ports of the parent entity. It mirrors the hardware hierarchy, and is used to build large systems from smaller, tested blocks.

3-bit up counter with T flip-flops

For a synchronous binary up counter, bit n toggles when all lower bits are 1:

• T0 = 1
• T1 = Q0
• T2 = Q0 . Q1

           Q0            Q1            Q2
 '1' -> T FF0 --+--> T FF1 --+     T FF2
                |            |      ^
                +--[ AND ]---+------+   (t2 = Q0 and Q1)
 clk drives the clock input of all three flip-flops

Components: tff (T flip-flop, rising-edge clock, asynchronous reset) and and2.

library ieee;
use ieee.std_logic_1164.all;

-- T flip-flop: toggles on the rising clock edge when t = '1'
entity tff is
  port (clk, rst, t : in std_logic; q : out std_logic);
end entity tff;

architecture behavioral of tff is
  signal q_int : std_logic := '0';
begin
  process (clk, rst)
  begin
    if rst = '1' then
      q_int <= '0';
    elsif rising_edge(clk) then
      if t = '1' then
        q_int <= not q_int;
      end if;
    end if;
  end process;
  q <= q_int;
end architecture behavioral;

library ieee;
use ieee.std_logic_1164.all;

-- 2-input AND gate
entity and2 is
  port (a, b : in std_logic; y : out std_logic);
end entity and2;

architecture dataflow of and2 is
begin
  y <= a and b;
end architecture dataflow;

library ieee;
use ieee.std_logic_1164.all;

-- 3-bit synchronous up counter, structural description
entity counter3 is
  port (
    clk : in  std_logic;
    rst : in  std_logic;
    q   : out std_logic_vector(2 downto 0)
  );
end entity counter3;

architecture structural of counter3 is
  component tff
    port (clk, rst, t : in std_logic; q : out std_logic);
  end component;
  component and2
    port (a, b : in std_logic; y : out std_logic);
  end component;

  signal q0, q1, q2 : std_logic;     -- flip-flop outputs
  signal t2         : std_logic;     -- T input of the third flip-flop
begin
  -- T0 = 1, T1 = Q0, T2 = Q0 . Q1
  ff0 : tff  port map (clk => clk, rst => rst, t => '1', q => q0);
  ff1 : tff  port map (clk => clk, rst => rst, t => q0,  q => q1);
  g1  : and2 port map (a => q0, b => q1, y => t2);
  ff2 : tff  port map (clk => clk, rst => rst, t => t2,  q => q2);

  q <= q2 & q1 & q0;
end architecture structural;

The design was analysed and simulated with GHDL: the output counts 0,1,2,...,7,0,1,2 on successive clock edges.