Mod-5 Gray code synchronous up counter

A mod-5 Gray code counter steps through the first five codes of the 3-bit Gray sequence, changing only one bit per clock:

$$000 \to 001 \to 011 \to 010 \to 110 \to 000$$

Step 1: Flip-flops and unused states

• 5 states need $n = 3$ JK flip-flops ($Q_2Q_1Q_0$), all clocked together on the negative (falling) edge.
• Unused states 100, 101 and 111 are treated as don't cares (X).

Step 2: Excitation table

JK excitation: 0→0: J=0, K=X; 0→1: J=1, K=X; 1→0: J=X, K=1; 1→1: J=X, K=0.

Step 3: K-maps

$K_2$: Q2 = 1 only in state 110, where it must reset, and the other cells are X, so $K_2 = 1$.

Step 4: Equations

$$\begin{aligned} &J_2 = Q_1\overline{Q_0},\quad K_2 = 1 \\ &J_1 = Q_0,\quad K_1 = Q_2 \\ &J_0 = \overline{Q_1},\quad K_0 = Q_1 \end{aligned}$$

Step 5: Circuit diagram

   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = Q1'    K0 = Q1
J1 = Q0     K1 = Q2
J2 = Q1.Q0' K2 = 1

Only one 2-input AND gate is needed, because $\overline{Q_1}$ and $\overline{Q_0}$ can be taken directly from the flip-flops' $\overline{Q}$ outputs.

Step 6: Check of unused states

All unused states enter the main sequence after one clock, so the counter is self-starting.

Step 7: Timing diagram (negative edge)

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾|___________
Q1   ________|‾‾‾‾‾‾‾‾‾‾‾|_______|‾‾‾
Q0   ____|‾‾‾‾‾‾‾|___________|‾‾‾‾‾‾‾
Cnt  000  001 011 010 110 000 001 011