Skip to main content

Sync vs async; mod-6 synchronous counter (JK)

Short answer

Synchronous counters have a common clock, so all flip-flops change simultaneously, offering high speed and no ripple delay. Asynchronous (ripple) counters cascade the clock, causing propagation delays. A MOD-6 synchronous counter uses states 000–101 with J0=K0=1, J1=Q2'Q0, K1=Q0, J2=Q1Q0, K2=Q0, and is self-starting.

Differentiate between synchronous and asynchronous counters. Design a mod-6 synchronous counter using JK flip-flops.

Synchronous vs asynchronous counters

PointSynchronous counterAsynchronous (ripple) counter
ClockCommon clock to all flip-flopsOnly FF0 gets the clock; each next FF is clocked by the previous output
Change of stateAll flip-flops change togetherFlip-flops change one after another (ripple)
DelayOne FF delay + gate delayAdds up: n×tpdn \times t_{pd}
SpeedFast, high clock frequencySlow, frequency falls as nn grows
CircuitNeeds extra gating logicSimple, few or no extra gates
Decoding glitchesNone (no false states)Momentary false states give glitches
Example ICs74160/74163, 741907490, 7493

Design of mod-6 synchronous counter (JK flip-flops)

Step 1: States. 000 → 001 → 010 → 011 → 100 → 101 → 000. Since 23=8≥62^3 = 8 \ge 6, three JK flip-flops (Q2Q1Q0Q_2Q_1Q_0) with a common clock are used. 110 and 111 are don't cares.

Step 2: Excitation table (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)

Present Q2Q1Q0Next Q2Q1Q0J2K2J1K1J0K0
0000010X0X1X
0010100X1XX1
0100110XX01X
0111001XX1X1
100101X00X1X
101000X10XX1

Step 3: K-maps

J1: Q2 / Q1Q000011110
001XX
100XX
K1: Q2 / Q1Q000011110
0XX10
1XXXX
J2: Q2 / Q1Q000011110
00010
1XXXX
K2: Q2 / Q1Q000011110
0XXXX
101XX

J0=K0=1J_0 = K_0 = 1 since Q0Q_0 toggles every clock.

Step 4: Equations

J2=Q1Q0,K2=Q0J1=Q2‾Q0,K1=Q0J0=1,K0=1\begin{aligned} &J_2 = Q_1Q_0,\quad K_2 = Q_0 \\ &J_1 = \overline{Q_2}Q_0,\quad K_1 = Q_0 \\ &J_0 = 1,\quad K_0 = 1 \end{aligned}

Step 5: Circuit diagram

   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = K0 = 1
J1 = Q2'.Q0    K1 = Q0
J2 = Q1.Q0     K2 = Q0

Step 6: Unused states: 110 → 111 → 000, so the counter is self-starting.

Step 7: Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾‾‾‾‾|_______
Q1   ________|‾‾‾‾‾‾‾|_______________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt  0    1   2   3   4   5   0   1

✓ Answer checked by Claude Opus 5.5 (high effort)

All Digital Logic chapter 8 questions →