- 2079 Bhadra · 2+7 marks
Sync vs async; mod-6 synchronous counter (JK)
Short answer
Synchronous counters have a common clock, so all flip-flops change simultaneously, offering high speed and no ripple delay. Asynchronous (ripple) counters cascade the clock, causing propagation delays. A MOD-6 synchronous counter uses states 000–101 with J0=K0=1, J1=Q2'Q0, K1=Q0, J2=Q1Q0, K2=Q0, and is self-starting.
Differentiate between synchronous and asynchronous counters. Design a mod-6 synchronous counter using JK flip-flops.
Synchronous vs asynchronous counters
| Point | Synchronous counter | Asynchronous (ripple) counter |
|---|---|---|
| Clock | Common clock to all flip-flops | Only FF0 gets the clock; each next FF is clocked by the previous output |
| Change of state | All flip-flops change together | Flip-flops change one after another (ripple) |
| Delay | One FF delay + gate delay | Adds up: |
| Speed | Fast, high clock frequency | Slow, frequency falls as grows |
| Circuit | Needs extra gating logic | Simple, few or no extra gates |
| Decoding glitches | None (no false states) | Momentary false states give glitches |
| Example ICs | 74160/74163, 74190 | 7490, 7493 |
Design of mod-6 synchronous counter (JK flip-flops)
Step 1: States. 000 → 001 → 010 → 011 → 100 → 101 → 000. Since , three JK flip-flops () with a common clock are used. 110 and 111 are don't cares.
Step 2: Excitation table (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)
| Present Q2Q1Q0 | Next Q2Q1Q0 | J2 | K2 | J1 | K1 | J0 | K0 |
|---|---|---|---|---|---|---|---|
| 000 | 001 | 0 | X | 0 | X | 1 | X |
| 001 | 010 | 0 | X | 1 | X | X | 1 |
| 010 | 011 | 0 | X | X | 0 | 1 | X |
| 011 | 100 | 1 | X | X | 1 | X | 1 |
| 100 | 101 | X | 0 | 0 | X | 1 | X |
| 101 | 000 | X | 1 | 0 | X | X | 1 |
Step 3: K-maps
| J1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 1 | X | X |
| 1 | 0 | 0 | X | X |
| K1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | 1 | 0 |
| 1 | X | X | X | X |
| J2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 |
| 1 | X | X | X | X |
| K2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | X | X |
| 1 | 0 | 1 | X | X |
since toggles every clock.
Step 4: Equations
Step 5: Circuit diagram
+-----+ +-----+ +-----+
J0>|J Q|-Q0 J1>|J Q|-Q1 J2>|J Q|-Q2
| FF0 | | FF1 | | FF2 |
K0>|K | K1>|K | K2>|K |
+--o--+ +--o--+ +--o--+
| | |
CLK---+-------------+-------------+
J0 = K0 = 1
J1 = Q2'.Q0 K1 = Q0
J2 = Q1.Q0 K2 = Q0
Step 6: Unused states: 110 → 111 → 000, so the counter is self-starting.
Step 7: Timing diagram
CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2 ________________|‾‾‾‾‾‾‾|_______
Q1 ________|‾‾‾‾‾‾‾|_______________
Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt 0 1 2 3 4 5 0 1
✓ Answer checked by Claude Opus 5.5 (high effort)
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