Sync vs async; mod-12 synchronous counter

Synchronous vs asynchronous sequential circuits

Mod-12 synchronous counter

It counts 0000 to 1011 (0–11) and returns to 0000. Four JK flip-flops share a common clock; states 1100–1111 are don't cares.

Excitation table

Equations (from K-maps)

$$\begin{aligned} &J_3 = Q_2Q_1Q_0,\quad K_3 = Q_1Q_0 \\ &J_2 = \overline{Q_3}Q_1Q_0,\quad K_2 = Q_1Q_0 \\ &J_1 = Q_0,\quad K_1 = Q_0 \\ &J_0 = 1,\quad K_0 = 1 \end{aligned}$$

Circuit diagram

   +-----+       +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2 J3>|J   Q|-Q3
   | FF0 |       | FF1 |       | FF2 |       | FF3 |
K0>|K    |    K1>|K    |    K2>|K    |    K3>|K    |
   +--o--+       +--o--+       +--o--+       +--o--+
      |             |             |             |
CLK---+-------------+-------------+-------------+
J0 = K0 = 1            J1 = K1 = Q0
J2 = Q3'.Q1.Q0  K2 = Q1.Q0
J3 = Q2.Q1.Q0   K3 = Q1.Q0

Operation

• $Q_0$ toggles on every clock edge.
• $Q_1$ toggles whenever $Q_0 = 1$.
• $Q_2$ sets when $Q_1Q_0 = 1$ and $Q_3 = 0$ (at 3 → 4), and resets when $Q_1Q_0 = 1$ (at 7 → 8). At 11 (1011), $Q_3 = 1$ blocks $J_2$, so $Q_2$ stays 0.
• $Q_3$ sets at 7 → 8 ($Q_2Q_1Q_0 = 1$) and resets at 11 → 0 ($Q_1Q_0 = 1$ with $Q_3 = 1$).
• So at the 12th clock, 1011 goes directly to 0000 with no false intermediate state.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    1   2   3   4   5   6   7   8   9   10  11  0

$Q_3$ is high for counts 8–11, giving $f_{clk}/12$. Unused states go 1100 → 1101 → 1110 → 1111 → 0000, so the counter is self-starting.