Asynchronous mod-12 up counter using JK

An asynchronous mod-12 up counter counts 0 to 11 and returns to 0 on the 12th clock pulse. Only FF0 is driven by the clock; the other flip-flops are driven by the previous stage.

Design steps

1. Flip-flops: $2^4 = 16 \ge 12$, so 4 JK flip-flops, all with $J = K = 1$ (toggle mode).
2. Clocking for positive-edge flip-flops: in an up count a stage must toggle when the previous output falls 1→0. A falling $Q$ is a rising $\overline{Q}$, so with positive-edge triggering each stage is clocked from the $\overline{Q}$ of the previous stage: CLK → FF0, $\overline{Q_0}$ → FF1, $\overline{Q_1}$ → FF2, $\overline{Q_2}$ → FF3.
3. Reset logic: count 12 = 1100 must clear the counter. It is the first state with $Q_3 = Q_2 = 1$, so

$$\overline{CLR} = \overline{Q_3\,Q_2}$$

A 2-input NAND gate feeds the active-low CLEAR of all four flip-flops.

Circuit diagram

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-> FF0 |Q0'-> FF1 |Q1'-> FF2 |Q2'-> FF3 |Q3
    +--o--+     +--o--+     +--o--+     +--o--+
      CLR         CLR         CLR         CLR

Q3  ---|      |
       | NAND |o--> CLR of all FFs (active low)
Q2  ---|      |

(">" marks a positive-edge clock input; the count is read from $Q_3Q_2Q_1Q_0$.)

Count sequence

Operation and timing

FF0 toggles at every rising clock edge. When $Q_0$ falls, $\overline{Q_0}$ rises and toggles FF1, and so on, giving an up count. On the 12th rising edge the counter reaches 1100, the NAND output goes low and clears all flip-flops to 0000.

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ______________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_____
Q2   ______________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_____________________
Q1   ______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_____
Q0   __|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|_____
Cnt  0  1   2   3   4   5   6   7   8   9   10  11  0

$Q_3$ is high for counts 8–11, so it gives $f_{clk}/12$.