Parallel counter; mod-6 synchronous counter (JK)

Parallel counter

A parallel counter is another name for a synchronous counter: the clock is applied to all flip-flops in parallel, so they all change state at the same instant. Gates at the J-K (or T/D) inputs decide which flip-flops toggle.

Design: mod-6 synchronous up counter (JK)

Step 1: States. A mod-6 counter counts 0 to 5 (000 to 101) and returns to 000. $2^3 = 8 \ge 6$, so 3 JK flip-flops ($Q_2Q_1Q_0$) are used. Unused states 110 and 111 are don't cares.

Step 2: Excitation table (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)

Step 3: K-maps

$J_0 = K_0 = 1$ since $Q_0$ toggles on every clock.

Step 4: Equations

$$\begin{aligned} &J_2 = Q_1Q_0,\quad K_2 = Q_0 \\ &J_1 = \overline{Q_2}Q_0,\quad K_1 = Q_0 \\ &J_0 = 1,\quad K_0 = 1 \end{aligned}$$

Step 5: Circuit diagram

   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = K0 = 1
J1 = Q2'.Q0     K1 = Q0
J2 = Q1.Q0      K2 = Q0

Two 2-input AND gates are needed.

Step 6: Unused states

So the counter is self-starting.

Step 7: Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾‾‾‾‾|_______
Q1   ________|‾‾‾‾‾‾‾|_______________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt  0    1   2   3   4   5   0   1

All outputs change together at the falling clock edge; $Q_2$ gives $f_{clk}/6$.