Mod-5 synchronous up counter using SR

A synchronous mod-5 up counter counts 000 → 001 → 010 → 011 → 100 → 000 with all flip-flops on one clock. Three SR flip-flops ($Q_2Q_1Q_0$) are needed ($2^3 = 8 \ge 5$); states 101, 110, 111 are don't cares.

Step 1: SR excitation

Step 2: Excitation table

Step 3: K-maps

For $R_2$, both $\overline{Q_1}$ and $\overline{Q_0}$ cover the 1-cell. With $R_2 = \overline{Q_1}$ the unused state 110 would hold itself forever (lock-out), so $R_2 = \overline{Q_0}$ is chosen.

Step 4: Equations

$$\begin{aligned} &S_2 = Q_1Q_0,\quad R_2 = \overline{Q_0} \\ &S_1 = \overline{Q_1}Q_0,\quad R_1 = Q_1Q_0 \\ &S_0 = \overline{Q_2}\overline{Q_0},\quad R_0 = Q_0 \end{aligned}$$

S and R of each flip-flop are never 1 together in any state, so the forbidden input S = R = 1 never occurs.

Step 5: Circuit diagram

   +-----+       +-----+       +-----+
S0>|S   Q|-Q0 S1>|S   Q|-Q1 S2>|S   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
R0>|R    |    R1>|R    |    R2>|R    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
S0 = Q2'.Q0'   R0 = Q0
S1 = Q1'.Q0    R1 = Q1.Q0
S2 = Q1.Q0     R2 = Q0'

Unused states: 101 → 110 → 010, 111 → 100, so the counter is self-starting.

Step 6: Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾|___________
Q1   ________|‾‾‾‾‾‾‾|___________|‾‾‾
Q0   ____|‾‾‾|___|‾‾‾|_______|‾‾‾|___
Cnt  0    1   2   3   4   0   1   2

$Q_2$ is high for one clock period in every five ($f_{clk}/5$).