Mod-6 synchronous up counter using T

A mod-6 synchronous counter goes through 6 states, 0 to 5 (000 to 101), and then returns to 000. Since $2^2 < 6 \le 2^3$, 3 T flip-flops (Q2 Q1 Q0, Q2 = MSB) with a common clock are used. A T flip-flop must have T = 1 whenever its output has to change.

Step 1: state diagram

 000 -> 001 -> 010 -> 011 -> 100 -> 101
  ^                                   |
  +-----------------------------------+
 Unused: 110, 111 (don't cares)

Step 2: T excitation table

Step 3: state table with flip-flop inputs

Step 4: K-maps

K-map for T2
Q2\Q1Q0  00  01  11  10
  0       0   0   1   0
  1       0   1   x   x

K-map for T1
Q2\Q1Q0  00  01  11  10
  0       0   1   1   0
  1       0   0   x   x

K-map for T0
Q2\Q1Q0  00  01  11  10
  0       1   1   1   1
  1       1   1   x   x

• $T_0$: all used states are 1, so $T_0 = 1$.
• $T_1$: 1s at states 1 and 3; state 5 is 0, so $T_1 = Q_0 \overline{Q_2}$.
• $T_2$: 1s at states 3 and 5; with don't care 7: $T_2 = Q_1 Q_0 + Q_2 Q_0$.

$$\begin{aligned} T_0 &= 1 \\ T_1 &= Q_0\,\overline{Q_2} \\ T_2 &= Q_0 Q_1 + Q_0 Q_2 = Q_0 (Q_1 + Q_2) \end{aligned}$$

Step 5: logic diagram

  1           T1            T2
  |           |             |
 +----+      +----+        +----+
 |T0  |      |T1  |        |T2  |
 | FF0|--Q0  | FF1|--Q1    | FF2|--Q2
 |>   |      |>   |        |>   |
 +----+      +----+        +----+
  ^           ^             ^
 CLK ---------+-------------+   (common clock)

 T1 = Q0 AND Q2'       : one 2-input AND
 T2 = Q0.Q1 + Q0.Q2    : two ANDs + one OR
                         (= Q0 AND (Q1 OR Q2))

Timing diagram

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Q0    _|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾
Q1    _____|‾‾‾‾‾‾‾|______________
Q2    _____________|‾‾‾‾‾‾‾|______

The output sequence is 000, 001, 010, 011, 100, 101, 000, ...; Q2 is high for two clocks out of six, so its frequency is $f_{CLK}/6$.

Unused states: 110 goes to 111 and 111 goes to 010, so the counter enters the main count by itself (self-starting).