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Synchronous decade counter with timing

Short answer

Use four T flip-flops. T0 = 1, T1 = Q3' Q0, T2 = Q1 Q0, T3 = Q3 Q0 + Q2 Q1 Q0. The counter sequences 0000 to 1001 then resets to 0000.

Design the synchronous decade counter using T flip-flop and also show its timing diagram.

A synchronous decade (BCD / mod-10) counter counts from 0000 to 1001 (0 to 9) and returns to 0000 on the 10th clock pulse. All flip-flops receive the same clock, so they change state together.

Step 1: Number of flip-flops and states

  • 10 states are needed, so 2n≥10⇒n=42^n \ge 10 \Rightarrow n = 4 T flip-flops (Q3Q2Q1Q0Q_3Q_2Q_1Q_0, Q0Q_0 = LSB).
  • Used states: 0000 to 1001. Unused states 1010 to 1111 are taken as don't cares (X).
  • T flip-flop excitation: T=Q⊕Q+T = Q \oplus Q^+ (T = 1 whenever the flip-flop must change).

Step 2: Excitation table

Present Q3Q2Q1Q0Next Q3Q2Q1Q0T3T2T1T0
000000010001
000100100011
001000110001
001101000111
010001010001
010101100011
011001110001
011110001111
100010010001
100100001001

Step 3: K-maps (X = don't care)

T0=1T_0 = 1 for every state. The other inputs:

T1: Q3Q2 / Q1Q000011110
000110
010110
11XXXX
1000XX
T2: Q3Q2 / Q1Q000011110
000010
010010
11XXXX
1000XX
T3: Q3Q2 / Q1Q000011110
000000
010010
11XXXX
1001XX

Step 4: Simplified equations

T3=Q3Q0+Q2Q1Q0T2=Q1Q0T1=Q3‾Q0T0=1\begin{aligned} &T_3 = Q_3Q_0 + Q_2Q_1Q_0 \\ &T_2 = Q_1Q_0 \\ &T_1 = \overline{Q_3}Q_0 \\ &T_0 = 1 \end{aligned}

So three 2-input AND gates (Q3‾Q0\overline{Q_3}Q_0, Q1Q0Q_1Q_0 and Q3Q0Q_3Q_0), one 3-input AND gate (Q2Q1Q0Q_2Q_1Q_0) and one 2-input OR gate (for T3T_3) are needed.

Step 5: Circuit diagram

   +-----+       +-----+       +-----+       +-----+
T0>|T   Q|-Q0 T1>|T   Q|-Q1 T2>|T   Q|-Q2 T3>|T   Q|-Q3
   | FF0 |       | FF1 |       | FF2 |       | FF3 |
   |     |       |     |       |     |       |     |
   +--o--+       +--o--+       +--o--+       +--o--+
      |             |             |             |
CLK---+-------------+-------------+-------------+
T0 = 1          T1 = Q3'.Q0
T2 = Q1.Q0      T3 = Q3.Q0 + Q2.Q1.Q0

Step 6: Timing diagram (negative-edge clock)

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾|_______
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt  0    1   2   3   4   5   6   7   8   9   0   1

Q0Q_0 toggles on every clock edge, Q1Q_1 toggles when Q0=1Q_0 = 1 (except at count 9), Q2Q_2 toggles when Q1Q0=1Q_1Q_0 = 1, and Q3Q_3 goes high at count 8 and returns low after count 9. The counter therefore divides the clock frequency by 10 (fQ3=fclk/10f_{Q_3} = f_{clk}/10).

Self-starting check: the unused states go back into the count (1010→1011→0110, 1100→1101→0100, 1110→1111→0010), so the counter cannot lock out.

✓ Answer checked by Claude Opus 5.5 (high effort)

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