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- 2076 Chaitra · 8 marks
- 2069 Chaitra · 8 marks
Synchronous decade counter with timing
Short answer
Use four T flip-flops. T0 = 1, T1 = Q3' Q0, T2 = Q1 Q0, T3 = Q3 Q0 + Q2 Q1 Q0. The counter sequences 0000 to 1001 then resets to 0000.
Design the synchronous decade counter using T flip-flop and also show its timing diagram.
A synchronous decade (BCD / mod-10) counter counts from 0000 to 1001 (0 to 9) and returns to 0000 on the 10th clock pulse. All flip-flops receive the same clock, so they change state together.
Step 1: Number of flip-flops and states
- 10 states are needed, so T flip-flops (, = LSB).
- Used states: 0000 to 1001. Unused states 1010 to 1111 are taken as don't cares (X).
- T flip-flop excitation: (T = 1 whenever the flip-flop must change).
Step 2: Excitation table
| Present Q3Q2Q1Q0 | Next Q3Q2Q1Q0 | T3 | T2 | T1 | T0 |
|---|---|---|---|---|---|
| 0000 | 0001 | 0 | 0 | 0 | 1 |
| 0001 | 0010 | 0 | 0 | 1 | 1 |
| 0010 | 0011 | 0 | 0 | 0 | 1 |
| 0011 | 0100 | 0 | 1 | 1 | 1 |
| 0100 | 0101 | 0 | 0 | 0 | 1 |
| 0101 | 0110 | 0 | 0 | 1 | 1 |
| 0110 | 0111 | 0 | 0 | 0 | 1 |
| 0111 | 1000 | 1 | 1 | 1 | 1 |
| 1000 | 1001 | 0 | 0 | 0 | 1 |
| 1001 | 0000 | 1 | 0 | 0 | 1 |
Step 3: K-maps (X = don't care)
for every state. The other inputs:
| T1: Q3Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 00 | 0 | 1 | 1 | 0 |
| 01 | 0 | 1 | 1 | 0 |
| 11 | X | X | X | X |
| 10 | 0 | 0 | X | X |
| T2: Q3Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 00 | 0 | 0 | 1 | 0 |
| 01 | 0 | 0 | 1 | 0 |
| 11 | X | X | X | X |
| 10 | 0 | 0 | X | X |
| T3: Q3Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 00 | 0 | 0 | 0 | 0 |
| 01 | 0 | 0 | 1 | 0 |
| 11 | X | X | X | X |
| 10 | 0 | 1 | X | X |
Step 4: Simplified equations
So three 2-input AND gates (, and ), one 3-input AND gate () and one 2-input OR gate (for ) are needed.
Step 5: Circuit diagram
+-----+ +-----+ +-----+ +-----+
T0>|T Q|-Q0 T1>|T Q|-Q1 T2>|T Q|-Q2 T3>|T Q|-Q3
| FF0 | | FF1 | | FF2 | | FF3 |
| | | | | | | |
+--o--+ +--o--+ +--o--+ +--o--+
| | | |
CLK---+-------------+-------------+-------------+
T0 = 1 T1 = Q3'.Q0
T2 = Q1.Q0 T3 = Q3.Q0 + Q2.Q1.Q0
Step 6: Timing diagram (negative-edge clock)
CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3 ________________________________|‾‾‾‾‾‾‾|_______
Q2 ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q1 ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______________
Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt 0 1 2 3 4 5 6 7 8 9 0 1
toggles on every clock edge, toggles when (except at count 9), toggles when , and goes high at count 8 and returns low after count 9. The counter therefore divides the clock frequency by 10 ().
Self-starting check: the unused states go back into the count (1010→1011→0110, 1100→1101→0100, 1110→1111→0010), so the counter cannot lock out.
✓ Answer checked by Claude Opus 5.5 (high effort)
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