Which pair correctly contrasts the two circuit types?

Combinational: no memory, output from present inputs; sequential: memory, output from inputs and past state

Combinational: has memory; sequential: no memory

Both depend only on present inputs

Sequential circuits never use a clock

Why is J1 = Q3'Q0 rather than just Q0?

To stop FF1 toggling at count 9 so the count returns to 0000 directly

Why does the synchronous decade counter show no false state after 1001?

All FFs share the clock and the gates give 0000 directly

A NAND gate clears it asynchronously

Asked 2/22
2080 Baisakh · 2+6 marks

Comb vs seq; synchronous decade counter

Short answer

Combinational circuits' outputs rely solely on current inputs; sequential circuits have memory. A synchronous decade counter connects all four JK flip-flops to one clock. With J0=K0=1, J1=Q3'Q0, K1=Q0, J2=K2=Q1Q0, J3=Q2Q1Q0, K3=Q0, it counts 0–9 and directly resets without ripple.

Differentiate between combinational and sequential logic circuits. Explain the operation of a synchronous decade counter with timing diagrams.

Combinational vs sequential logic circuits

Point	Combinational circuit	Sequential circuit
Output depends on	Present inputs only	Present inputs and past state
Memory	No memory	Has memory (flip-flops/latches)
Feedback	No feedback path	Feedback from output to input
Clock	Not needed	Usually clocked
Analysis tool	Truth table	State table / state diagram
Examples	Adder, MUX, decoder	Flip-flop, register, counter

Synchronous decade counter

A synchronous decade counter counts 0000 to 1001 with all four flip-flops clocked together. Gates decide when each flip-flop toggles. From the excitation table of the 0–9 sequence (states 1010–1111 as don't cares), the JK equations are:

\begin{aligned} &J_3 = Q_2Q_1Q_0,\quad K_3 = Q_0 \\ &J_2 = Q_1Q_0,\quad K_2 = Q_1Q_0 \\ &J_1 = \overline{Q_3}Q_0,\quad K_1 = Q_0 \\ &J_0 = 1,\quad K_0 = 1 \end{aligned}

Circuit diagram

   +-----+       +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2 J3>|J   Q|-Q3
   | FF0 |       | FF1 |       | FF2 |       | FF3 |
K0>|K    |    K1>|K    |    K2>|K    |    K3>|K    |
   +--o--+       +--o--+       +--o--+       +--o--+
      |             |             |             |
CLK---+-------------+-------------+-------------+
J0 = K0 = 1        J1 = Q3'.Q0   K1 = Q0
J2 = K2 = Q1.Q0    J3 = Q2.Q1.Q0  K3 = Q0

Operation

Count	Q3 Q2 Q1 Q0	Flip-flops that toggle at next clock
0	0000	FF0
1	0001	FF0, FF1
2	0010	FF0
3	0011	FF0, FF1, FF2
4	0100	FF0
5	0101	FF0, FF1
6	0110	FF0
7	0111	FF0, FF1, FF2, FF3 (set)
8	1000	FF0
9	1001	FF0, FF3 (reset); FF1 held by $\overline{Q_3} = 0$

FF0 toggles on every clock ( $J_0 = K_0 = 1$ ).
FF1 toggles when $Q_0 = 1$ , but at count 9 $J_1 = \overline{Q_3}Q_0 = 0$ keeps it at 0.
FF2 toggles when $Q_1Q_0 = 1$ .
FF3 sets when $Q_2Q_1Q_0 = 1$ (7 → 8) and resets when $Q_0 = 1$ while $Q_3 = 1$ (9 → 0).

So after count 9 (1001) the next clock gives 0000 directly, without any false state.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾|_______
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt  0    1   2   3   4   5   6   7   8   9   0   1

All outputs change at the same falling edge, so there is no ripple delay. $Q_3$ gives $f_{clk}/10$ .

✓ Answer checked by Claude Opus 5.5 (high effort)

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