Comb vs seq; asynchronous decade counter

Combinational vs sequential circuits

Asynchronous decade counter

It counts 0000 to 1001 (0–9) and resets on the 10th pulse.

Circuit: four negative-edge JK flip-flops with $J = K = 1$. CLK → FF0; $Q_0$, $Q_1$, $Q_2$ clock FF1, FF2, FF3. A NAND of $Q_3$ and $Q_1$ drives the active-low CLEAR of all flip-flops.

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3
    +--o--+     +--o--+     +--o--+     +--o--+
      CLR         CLR         CLR         CLR

Q3  ---|      |
       | NAND |o--> CLR of all FFs (active low)
Q1  ---|      |

Operation

1. Start at 0000. FF0 toggles on every falling clock edge.
2. FF1 toggles when $Q_0$ goes 1→0, FF2 when $Q_1$ goes 1→0, FF3 when $Q_2$ goes 1→0, so the count rises by one per pulse: 0, 1, …, 9.
3. On the 10th pulse the outputs try to become 1010. Since $Q_3 = Q_1 = 1$, the NAND output goes low and clears all flip-flops to 0000. The 1010 state lasts only a few nanoseconds.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾|___
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    1   2   3   4   5   6   7   8   9   0

$Q_3$ is high for counts 8 and 9 and gives $f_{clk}/10$. Example IC: 7490.