- 2082 Shrawan · 2+6 marks
Synchronous vs asynchronous circuits; SR to JK
Short answer
Synchronous circuits change state only at clock edges using a common clock; asynchronous circuits respond immediately to input changes without a clock and suffer from race conditions. Convert SR to JK by deriving S = J Q' and R = K Q from excitation and K-map; implement with AND gates feeding the SR’s S and R inputs.
Differentiate between synchronous and asynchronous sequential logic circuits. How to convert SR flip-flop into JK flip-flop?
Synchronous vs asynchronous sequential circuits
| Point | Synchronous sequential | Asynchronous sequential |
|---|---|---|
| State change | Only at clock edges | Whenever inputs change |
| Clock | Common clock needed | No clock (or not common) |
| Memory elements | Clocked flip-flops | Latches / delay elements |
| Speed | Limited by clock rate | Faster |
| Design | Easier, reliable | Harder; races and hazards |
| Example | Synchronous counter | Ripple counter, SR latch |
Converting S-R flip-flop into J-K flip-flop
Step 1: excitation table of the available S-R flip-flop
| Q | Q+ | S | R |
|---|---|---|---|
| 0 | 0 | 0 | x |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | x | 0 |
Step 2: conversion table. For each J, K and present state Q, find Q+ from the J-K characteristic table, then write the S and R needed for that change:
| J | K | Q | Q+ | S | R |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | x |
| 0 | 0 | 1 | 1 | x | 0 |
| 0 | 1 | 0 | 0 | 0 | x |
| 0 | 1 | 1 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 1 | x | 0 |
| 1 | 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 |
Step 3: K-maps
K-map for S
Q\JK 00 01 11 10
0 0 0 1 1
1 x 0 0 x
K-map for R
Q\JK 00 01 11 10
0 x x 0 0
1 0 1 1 0
- S: the 1s are at Q = 0, JK = 11 and 10; the don't-cares at Q = 1 cannot enlarge this group (Q = 1, JK = 11 is 0), so .
- R: the 1s are at Q = 1, JK = 01 and 11, so .
Step 4: circuit
+-----+ +---------+
J -------->| | | |
Q' ------->| AND |----->| S Q |---> Q
+-----+ | |
+-----+ CLK->|> SR |
K -------->| | | |
Q ------->| AND |----->| R Q' |---> Q'
+-----+ +---------+
(Q and Q' are fed back from the outputs)
Check: J = K = 1 with Q = 0 gives S = 1, R = 0 (Q becomes 1); with Q = 1 gives S = 0, R = 1 (Q becomes 0). So the circuit toggles, and S = R = 1 can never occur because S needs Q = 0 while R needs Q = 1.
✓ Answer checked by Claude Opus 5.5 (high effort)
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