Asynchronous (ripple) decade counter

An asynchronous (ripple) decade counter is a mod-10 ripple counter: it counts 0000 to 1001 and resets to 0000 on the 10th clock pulse.

Design

• Number of flip-flops: $2^n \ge 10 \Rightarrow n = 4$ JK flip-flops, negative-edge triggered, all with $J = K = 1$ (toggle mode).
• The clock drives FF0 only; $Q_0$ clocks FF1, $Q_1$ clocks FF2, $Q_2$ clocks FF3.
• The counter must reset when the count reaches 10 = 1010. In 1010, $Q_3 = 1$ and $Q_1 = 1$; this is the first count in which both are 1. So a 2-input NAND gate of $Q_3$ and $Q_1$ drives the active-low CLEAR inputs of all flip-flops.

Circuit diagram

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3
    +--o--+     +--o--+     +--o--+     +--o--+
      CLR         CLR         CLR         CLR

Q3  ---|      |
       | NAND |o--> CLR of all FFs (active low)
Q1  ---|      |

Count sequence

Operation

On each falling clock edge FF0 toggles. Each later flip-flop toggles when the previous output falls from 1 to 0, so the count goes up by one per clock. At the 10th pulse the counter momentarily enters 1010; NAND output goes low and clears all flip-flops to 0000 within a few nanoseconds. The state 1010 lasts only for this short time, so the counter shows 0 to 9.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾|___
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    1   2   3   4   5   6   7   8   9   0

(A very short spike on $Q_1$ at the 10th edge, caused by the 1010 state, is ignored in the ideal diagram.) $Q_3$ has a frequency of $f_{clk}/10$, so the circuit is also a divide-by-10 circuit. IC 7490 is a ready-made decade ripple counter.