SISO register with 1101 data

A 4-bit serial-in serial-out (SISO) shift register is four D flip-flops connected in a chain with a common clock. Data enters one bit per clock at the first flip-flop and comes out one bit per clock from the last flip-flop.

Circuit

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-->|D  QB|-->|D  QC|-->|D  QD|--> Dout
      |>    |   |>    |   |>    |   |>    |
      +-----+   +-----+   +-----+   +-----+
         ^         ^         ^         ^
 CLK ----+---------+---------+---------+

Data enters FF-A only and leaves from FF-D only. At each rising edge: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$.

Operation with data 1101

The register is cleared to 0000 first. The data is entered LSB first: serial input = 1, 0, 1, 1 at clocks 1 to 4, then 0s.

• Storing (clocks 1 to 4): after clock 4, QA QB QC QD = 1101, i.e. 1101 is held with QA as MSB.
• Retrieving (serial out at QD): the output after clocks 4, 5, 6, 7 is 1, 0, 1, 1, which is 1101 read LSB first. After clock 8 the register is empty again.
• A 4-bit SISO register needs 4 clocks to load and 4 clocks to empty (3 more clocks after the first bit appears).

Timing diagram

       1   2   3   4   5   6   7   8
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Din   ‾‾‾|___|‾‾‾‾‾‾‾|________________
QA    _|‾‾‾|___|‾‾‾‾‾‾‾|______________
QB    _____|‾‾‾|___|‾‾‾‾‾‾‾|__________
QC    _________|‾‾‾|___|‾‾‾‾‾‾‾|______
QD    _____________|‾‾‾|___|‾‾‾‾‾‾‾|__

Each Q waveform is the previous one delayed by one clock period.

Uses: delaying a serial signal by 4 clock periods and serial data transfer.