4-bit bidirectional shift register

A bidirectional shift register can shift its data either to the right or to the left, selected by a mode control line RIGHT/LEFT' (M). It uses four D flip-flops with a common clock and a 2-to-1 AND-OR selector in front of each D input.

Circuit

 One stage (stage B) of the register:
 QA ------------->+-----+
 R/L' ---+------->| AND |--+
         |        +-----+  |  +----+
         |                 +->| OR |--> DB
         |        +-----+  +->|    |
         +-[NOT]->| AND |--+  +----+
 QC ------------->+-----+
 DB = M.QA + M'.QC        (M = R/L')

 Full register:
 DR ->[sel]->FF-A <-> [sel]->FF-B <-> [sel]->FF-C
       <-> [sel]->FF-D <-[sel]<- DL
 DA = M.DR + M'.QB     DB = M.QA + M'.QC
 DC = M.QB + M'.QD     DD = M.QC + M'.DL

• M = 1 (shift right): the upper AND gates are enabled. Each flip-flop takes the output of the stage on its left: $QA \leftarrow DR,\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$. Serial data enters at DR and leaves at QD.
• M = 0 (shift left): the lower AND gates are enabled. Each flip-flop takes the output of the stage on its right: $QD \leftarrow DL,\ QC \leftarrow QD,\ QB \leftarrow QC,\ QA \leftarrow QB$. Serial data enters at DL and leaves at QA.

Truth (function) table

Example and timing diagram

Starting from 0000: shift right for 4 clocks with DR = 1, 0, 1, 1; then shift left for 3 clocks with DL = 0, 1, 1.

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
R/L'  ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|____________
DR    ‾‾‾|___|‾‾‾‾‾‾‾|____________
DL    ___________________|‾‾‾‾‾‾‾|
QA    _|‾‾‾|___|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾
QB    _____|‾‾‾|___|‾‾‾|___|‾‾‾|__
QC    _________|‾‾‾|___|‾‾‾|___|‾‾
QD    _____________|‾‾‾|___|‾‾‾‾‾‾

During clocks 1 to 4 the bits move towards QD; from clock 5 the direction reverses and the bits move towards QA while new bits enter at QD. Bidirectional (universal) shift registers such as IC 74194 are used for multiplication/division by 2 and in serial data handling.