Microprocessor based system and bus organization

A microprocessor based system is a computer system built around a microprocessor (CPU) together with memory and input/output devices, all connected by buses.

 +-------+
 | Clock |
 +---+---+
     |
 +---+---+   +--------+   +--------+   +--------+
 |  CPU  |   | ROM    |   | RAM    |   | I/O    |
 | (MPU) |   |        |   |        |   | devices|
 +---+---+   +---+----+   +---+----+   +---+----+
     |           |   chip select  |            |
     |       +---+----------------+------------+---+
     |       |          Address decoder            |
     |       +-----------------+-------------------+
     |                         |
 ====+=========================+===================== Address bus
 ====+============================================== Data bus
 ====+============================================== Control bus
 (ROM, RAM and I/O also connect to all three buses)

Parts of the system

• Microprocessor (CPU): the brain. It has the ALU (arithmetic and logic operations), registers (temporary storage), and the control unit (fetches, decodes and generates timing/control signals).
• Memory: stores programs and data. ROM holds permanent programs (e.g., boot/monitor program) and is non-volatile. RAM holds the user program and data being processed and is volatile.
• Input/Output devices: connect the system to the outside world. Input devices (keyboard, switches, sensors) send data in; output devices (display, printer, LEDs) take data out. They are connected through interface chips (ports) such as 8255.
• Buses: groups of wires that carry information between the parts.

Bus organization

1. Address bus: unidirectional; carries the address of the memory location or I/O port from the CPU. An n-bit address bus can address 2ⁿ locations (8085: 16 lines, 64 KB).
2. Data bus: bidirectional; carries data between CPU, memory and I/O. Its width (8 bits in 8085) gives the word length.
3. Control bus: carries control and timing signals such as RD, WR, IO/M, ALE, INTR, HOLD, READY, so that only the selected device responds and data flows in the right direction at the right time.

On the 8085 the lower address lines are multiplexed with the data bus (AD0-AD7). In T1 of each machine cycle the CPU puts the low address byte on AD0-AD7 and raises ALE; an external latch (e.g. 74LS373) holds it as A0-A7. From T2 the same lines carry data. A8-A15 carry the high address byte throughout.

When a device such as a DMA controller raises HOLD, the CPU finishes its current cycle, answers with HLDA and tri-states its buses so the other device can use them.

The CPU puts an address on the address bus; the address decoder selects one device; the control bus tells whether to read or write; and data moves on the data bus.