- 2070 Bhadra · 4+4 marks
Bus, bus types and RTL for MOV
Short answer
A bus is a group of parallel conductors. The unidirectional address bus selects a memory/IO location; the bidirectional data bus carries data/instructions; the control bus handles read/write and timing signals. RTL uses symbolic notation: MOV r1,r2 fetches the opcode (IR←M[PC], PC+1) and then performs r1←r2 in the same machine cycle.
Define bus. Explain different types of bus. Define RTL. Write down the RTL for MOV r1, r2 in 8085 microprocessor.
Bus
A bus is a group of parallel conductors (wires) used to carry binary information (address, data or control signals) between the microprocessor, memory and I/O devices.
Types of bus
- Address bus: unidirectional (CPU to others). It carries the address of the memory location or I/O port. With n lines, 2ⁿ locations can be addressed. The 8085 has a 16-bit address bus (A0-A15), so it can address 64 KB.
- Data bus: bidirectional. It carries data and instruction codes between the CPU and memory/I/O. Width decides the word size; the 8085 has an 8-bit data bus (D0-D7, multiplexed with A0-A7 as AD0-AD7).
- Control bus: carries signals that coordinate operations. Examples are RD, WR, IO/M, ALE, READY, HOLD, HLDA, INTR, INTA. Some are outputs from the CPU, some are inputs to it.
RTL
Register Transfer Language (RTL) is a symbolic notation that describes the micro-operations of a processor as data transfers between registers or between registers and memory, e.g., A <- B, MDR <- M[MAR].
RTL for MOV r1, r2
MOV r1,r2 copies the contents of register r2 into r1. It is a 1-byte instruction (01 DDD SSS) and takes one machine cycle (opcode fetch) of 4 T-states in the 8085.
M1 (opcode fetch, 4 T-states):
T1-T3: IR <- M[PC] ; PC <- PC + 1 ; read the opcode 01DDDSSS
T4: decode IR, then r1 <- r2 ; no further memory access
Example: MOV A,B has opcode 78H; after execution A has the value of B and B is unchanged.
✓ Answer checked by Claude Opus 5.5 (high effort)
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