Internal architecture of 8086

 +---------------- BIU ----------------+
 |  CS   DS   SS   ES   (segment regs) |
 |  IP  (instruction pointer)          |
 |  Address adder  -> 20-bit address   |
 |  6-byte instruction queue           |
 |  Bus control logic                  |
 +------------------+------------------+
                    | internal bus
 +------------------+------------------+
 |  AX BX CX DX  (general registers)   |
 |  SP BP SI DI  (pointer/index)       |
 |  ALU      FLAG register             |
 |  Control unit + instruction decoder |
 +---------------- EU -----------------+
   BIU <-> external bus: AD0-AD15, A16-A19, control

The 8086 is a 16-bit microprocessor with a 16-bit data bus and a 20-bit address bus (1 MB of memory). Internally it is divided into two independent units, the Bus Interface Unit (BIU) and the Execution Unit (EU), which work in parallel (pipelining).

Bus Interface Unit (BIU)

Handles all external bus operations: fetching instructions, reading and writing memory and I/O.

• Segment registers CS, DS, SS, ES: hold the base of the code, data, stack and extra segments.
• Instruction pointer (IP): offset of the next instruction in the code segment.
• Address adder: physical address = (segment × 10H) + offset, giving 20 bits.
• Instruction queue: 6-byte FIFO. The BIU pre-fetches instructions while the EU executes, so the EU rarely waits.
• Bus control logic: generates address, data and control signals; the AD0–AD15 lines are multiplexed.

Execution Unit (EU)

Decodes and executes instructions; it has no direct connection to the outside world.

• General purpose registers AX, BX, CX, DX (each splits into 8-bit halves, e.g. AH/AL).
• Pointer and index registers SP, BP, SI, DI.
• ALU: 16-bit arithmetic and logic operations.
• Flag register: 9 flags (CF, PF, AF, ZF, SF, OF, TF, IF, DF).
• Control unit and decoder: takes opcodes from the queue, decodes them and generates control signals for the ALU and registers.

When the EU needs data from memory or I/O, it asks the BIU to transfer it. Whenever at least 2 bytes of the queue are free, the BIU fetches the next instruction bytes.