Interfacing: 512-byte RAM with 8085

Interfacing means connecting a memory or I/O device to the microprocessor buses (address, data, control) with the necessary decoding and buffering logic, so that the processor can access the device at a defined address and with proper timing.

Design: 512 x 8 RAM with 8085

A 512-byte chip needs 9 address lines (2^9 = 512), A0-A8. The remaining lines A15-A9 (7 lines) are decoded for chip select. Assume the RAM is placed at 0000H-01FFH.

 A15 A14 A13 A12 A11 A10 A9 ---+
 IO/M --------------------------+--[ 8-input OR ]--> CS' of RAM
 A8..A0 ---------------------------------> A8..A0 of RAM
 RD' -> OE'      WR' -> WE'
 AD0-AD7 -> 74LS373 (ALE) -> A0-A7      D0-D7 <-> AD0-AD7 data

CS' is active low. The output of an OR gate is low only when all its inputs are low, so CS' is low only when A15-A9 = 0 and IO/M = 0 (memory cycle). An equivalent circuit is a 7-input NOR of A15-A9 (output 1 when all are 0) followed by a NAND with the inverted IO/M.

With a 74LS138: connect A11, A10, A9 to the select inputs C, B, A, and enable the decoder with G1 = NOR(A15, A14, A13, A12), G2A' = IO/M and G2B' = 0. Output Y0' is then the chip select for 0000H-01FFH (Y1' for 0200H-03FFH, and so on).

This is full decoding, so the RAM responds only to 0000H-01FFH. During a read, RD' enables the RAM output; during a write, WR' writes the data on D0-D7.