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Interfacing 8-channel 8-bit ADC with 8085

Short answer

ADC0808 is interfaced to 8085 via I/O port 80H: OUT 80H pulses ALE and START together with channel number on D0–D2; after EOC rises (~100 µs), IN 80H enables OE and reads the 8-bit data. Clock is 640 kHz, resolution 19.5 mV per count.

With necessary diagram, Explain interfacing of 8 channel 8 bit ADC with 8085 microprocessor along with timing diagram.

The ADC0808/0809 is an 8-bit successive approximation ADC with an 8-channel analog multiplexer. It needs a clock (10-1280 kHz, typically 640 kHz), and has control pins ADD A, B, C (channel select), ALE (address latch enable), START, EOC (end of conversion) and OE (output enable).

Interfacing (I/O mapped, port 80H)

 Analog IN0-IN7 ->+-------------+
                  |  ADC 0808   |-- D0-D7 --> AD0-AD7 (via IN)
 8085 D0-D2 ----->| ADD A,B,C   |
 IOW' + A7..A0    | ALE & START |<-- from decoder (OUT 80H)
 decoder (80H) -->|             |
 IOR' + decoder ->| OE          |
 RST 5.5 / polled<-| EOC        |
 CLK OUT / 4 ---->| CLK 640 kHz |
                  | Vref+=5V, Vref-=0
                  +-------------+

OUT 80H puts the channel number on D0-D2 and gives a pulse on ALE and START together; IN 80H makes OE high and reads the data. EOC can be read through an input buffer (polling) or connected to an interrupt input.

Timing diagram

 ADD A,B,C ---< channel valid >-----------------------
 ALE       ______/------\______________________________
 START     ______/------\______________________________
 EOC       -------------\_____________________/--------
                         |<-- conversion ~100us -->|
 OE        _________________________________/-----\____
 D0-D7     -------------------------------< valid >----
  1. Address is valid; ALE goes high and latches it.
  2. START: the rising edge resets the ADC, the falling edge begins conversion; EOC falls (within 8 clock periods).
  3. After about 100 us, EOC rises.
  4. OE goes high; data appears on D0-D7 (output delay about 250 ns); the CPU reads it.

Program

        MVI A,03H       ; channel 3
        OUT 80H         ; address, ALE, START
        MVI C,FFH
DELAY:  DCR C
        JNZ DELAY       ; wait more than 100 us (or poll EOC)
        IN 80H          ; read data (OE active)
        STA 2050H
        HLT

Resolution: 5 V / 256 = 19.5 mV per count.

✓ Answer checked by Claude Sonnet 5.5

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