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Dual slope ADC block diagram; integral linearity

Short answer

Dual-slope ADC integrates the input for fixed time T1, then de-integrates with a reference until zero; the counter output N2 = N1 * Vin / Vref. Integral linearity (INL) of a DAC is the maximum deviation of the actual output from the ideal straight line after removing offset and gain errors, measured in LSB.

Draw the block diagram of Dual-slope type ADC and explain about its working principle with necessary diagram. Explain briefly about integral linearity of the DAC.

A dual slope ADC is an integrating ADC. It integrates the unknown input for a fixed time, then integrates a reference of opposite polarity until the integrator output returns to zero. The time taken for the second part is proportional to the input.

Block diagram

 Vin  --o S1                 C
 -Vref--o--+--[R]--+--------||--------+
                   |                  |
                  (-)\                |
                      >---------------+--Vo1-->[COMPARATOR]
                  (+)/                              |
                   |                                v
                  GND        CLOCK-->[COUNTER]<-->[CONTROL]
                                        |
                                   digital out

Working

  1. Reset: the counter is cleared and the capacitor is discharged (Vo1 = 0).
  2. Integration (fixed time T1): S1 connects Vin. The integrator output ramps at a slope set by Vin/RC, while the counter counts a fixed N1 = 2ⁿ pulses. So T1 = N1·Tclk.
Vo1(T1) = −Vin·T1 / RC
  1. De-integration (variable time T2): when the counter overflows, it resets and S1 switches to −Vref (opposite polarity). The output ramps back towards zero at a fixed slope Vref/RC, and the counter counts again.
  2. Stop: when Vo1 reaches zero, the comparator changes state and the control logic stops the counter. Then:
Vin·T1 / RC = Vref·T2 / RC
T2 = T1·Vin / Vref,   N2 = N1·Vin / Vref

The count N2 is the digital output.

 |Vo1|
  |    /\          (larger Vin: steeper up-ramp)
  |   /  \
  |  /    \     same down-slope (Vref fixed)
  | /      \
  |/________\_____ t
  |<- T1 ->|<T2>|

R, C and the clock frequency cancel out, so the converter is accurate. Integration also averages out noise. It is slow (tens of ms) and used in digital voltmeters.

Integral linearity of a DAC

Integral linearity (integral non-linearity, INL) is the maximum deviation of the actual DAC transfer curve from the ideal straight line joining zero and full scale. It is measured in LSB or % of full scale, after removing offset and gain error.

  • Ideal: each output level lies exactly on the straight line Vo = D × LSB.
  • INL = max |Vactual(D) − Videal(D)|, for example ±½ LSB.
  • It is caused by resistor mismatch and switch resistance. A small INL means the output is proportional to the code over the whole range.

✓ Answer checked by Claude Opus 5.5 (high effort)

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