Digital-to-Analog and Analog-to-Digital Conversion

A dual slope ADC is an integrating ADC. It integrates the unknown input for a fixed time and then integrates a known reference of opposite polarity until the integrator returns to zero. The time taken in the second phase, measured by a counter, is proportional to the input.

        S1
 Vin --o\      R        C
         o---/\/\/--+--||--+
 -Vref -o/          |       |
                    +-(-)   |
               GND --(+)>---+-- Vo1 --+
                   integrator         |
                                 comparator
                                (Vo1 vs 0 V)
                                      |
 clock --> [ control logic ] <--------+
                 |      |
            switch S1  [ n-bit counter ] -> digital
                                            output

Working

1. Reset: the counter is cleared and the capacitor is discharged, so Vo1 = 0.
2. Phase 1 (fixed time T1): S1 connects Vin (positive) to the integrator. The output ramps down with slope −Vin/RC. The counter counts until it overflows after N1 = 2ⁿ clock pulses, so T1 = 2ⁿ·Tc (fixed).

Vo1(T1) = -Vin·T1/(RC)

3. Phase 2 (variable time T2): at overflow the control logic switches S1 to −Vref and the counter restarts from zero. The output now ramps up with fixed slope Vref/RC. When Vo1 reaches 0 V the comparator changes state and the counter stops at N2.

Vin·T1/(RC) = Vref·T2/(RC)
T2 = T1·Vin/Vref
N2·Tc = N1·Tc·Vin/Vref
N2 = 2ⁿ · Vin / Vref

The count N2 is the digital output and is directly proportional to Vin.

Vo1
 0 +--.                      .----
   |   \  slope -Vin/RC     /
   |    \                  / slope Vref/RC
   |     \_______________/  (fixed)
   |<--  T1 fixed -->|<- T2 ->|

Why the output is accurate

• R, C and clock frequency cancel: they appear on both sides of Vin·T1/RC = Vref·T2/RC, and the same clock times both phases, so their tolerance, drift and ageing do not affect the result. Accuracy depends only on Vref.
• Noise rejection: the input is averaged over T1, so random noise is reduced. If T1 is a multiple of the mains period (20 ms for 50 Hz), mains hum integrates to zero.
• Comparator offset has little effect because the comparator only detects the zero crossing at the same level each time.
• Good linearity, no missing codes, and high resolution are possible.

The disadvantage is low speed (tens of conversions per second), so it is used in digital multimeters and panel meters.

An inverted (current-mode) R-2R ladder DAC uses only two resistor values, R and 2R. Each 2R leg is switched either to the virtual ground of the op-amp (bit = 1) or to real ground (bit = 0). Since both positions are at 0 V, the ladder currents never change.

 Vref     R        R        R
  o--+--/\/\--+--/\/\--+--/\/\--+-----+
     |        |        |        |     |
     2R       2R       2R       2R    2R
     | I/2    | I/4    | I/8    | I/16 |
    [S1]     [S2]     [S3]     [S4]  GND
   (MSB)                     (LSB)
 bit = 1: switch to Iout bus
 bit = 0: switch to GND

             Rf
   Iout  +--/\/\--+
   bus --+--(-)   |
              >---+--- Vo
      GND ---(+)

Derivation (n-bit)

1. Looking right from any node, the resistance is 2R in parallel with 2R = R, plus R in series gives 2R again. So the total resistance seen by Vref is R, and

I = Vref / R

2. At each node the current splits equally between the 2R leg and the rest of the ladder (both are 2R to ground potential). So the leg currents are

I1 = I/2, I2 = I/4, I3 = I/8, ... In = I/2ⁿ

3. Bit bk = 1 sends Ik to the summing bus (virtual ground); bk = 0 sends it to ground.

Iout = (Vref/R) [b1/2 + b2/4 + b3/8 + ... + bn/2ⁿ]

4. The op-amp converts this current to voltage:

Vo = -Rf · Iout
   = -(Rf/R) · Vref · [b1·2⁻¹ + b2·2⁻² + ... + bn·2⁻ⁿ]
   = -(Rf/R) · Vref · D/2ⁿ

where D is the decimal value of the input (b1 = MSB). With Rf = R, 4-bit, Vref = 10 V and input 1010: Vo = −10 × 10/16 = −6.25 V.

Advantages of the R-2R type DAC

• Only two resistor values (R and 2R), easy to make and match accurately in ICs, regardless of the number of bits.
• Easily expanded to more bits by adding R-2R sections.
• Constant current in each leg and constant load on Vref (inverted type), since switches only move current between two 0 V points.
• High speed and fewer glitches: node voltages do not change, so stray capacitances are not charged and discharged.
• Good accuracy and temperature tracking; resistor values stay in a practical range (unlike the weighted-resistor DAC).

Bipolar DAC

A bipolar DAC gives an output of both polarities (−FS/2 to +FS/2) instead of 0 to +FS. It is needed for signals such as audio and for systems that use offset-binary or 2's-complement codes.

Method (offset binary): a unipolar DAC is used and a fixed offset current equal to half of full scale is subtracted at the summing node, so the output is shifted down by FS/2.

 -Vref -> R-2R ladder (b1..bn) --Iout--+
                                       |
 +Vref ----2R---- Ioff ----------------+
                                       |     Rf
                                       +---/\/\/--+
                                       |          |
                                       +--(-)     |
                                 GND -----(+) >---+-- Vo

Ladder current (reference -Vref): Iout = -(Vref/R)·D/2ⁿ
Offset current: Ioff = Vref/(2R)
Vo = -Rf (Iout + Ioff)
   = (Rf/R)·Vref·(D/2ⁿ - 1/2)

With Rf = R, Vref = 8 V and 3 bits: Vo = 8(D/8 − 1/2) = (D − 4) V.

So the MSB acts as a sign bit (1 = positive, 0 = negative). Inverting the MSB converts 2's-complement input to offset binary. The output range is −FS/2 to +FS/2 − 1 LSB.

Disadvantages of the weighted-resistor DAC

• Wide range of resistor values: R, 2R, 4R, …, 2ⁿ⁻¹R. For 12 bits the largest is 2048R, e.g. 10 kΩ to 20.48 MΩ.
• Hard to make accurately in ICs: very large and very small resistors, each needing a different precision, are hard to fabricate and match.
• MSB resistor needs the highest accuracy (tolerance better than 1/2ⁿ), which is difficult and costly.
• Switch resistance error: the switch on-resistance is significant compared with the small MSB resistor.
• Poor temperature tracking of resistors of very different values.
• Current drawn from Vref changes with the input code, loading the reference.
• So it is practical only up to about 6 to 8 bits; the R-2R ladder is preferred.

In a dual slope ADC the input is integrated for a fixed time T1 (fixed number of clock pulses N1), then the reference is integrated back to zero. The count N2 taken in the de-integration time T2 is the digital output.

Given

• Clock frequency f = 12 kHz, so clock period T = 1/f = 1/12000 = 83.33 µs
• Fixed count for T1: N1 = 1000 pulses
• Vref = 100 mV, Vin = 100 mV

Basic relation

During T1 the integrator output reaches Vin·T1/RC. During T2 it falls back to zero at slope Vref/RC. Equating:

Vin·T1 / RC = Vref·T2 / RC
T2 = T1 · (Vin / Vref)
N2 = N1 · (Vin / Vref)

The RC value cancels, so it is not needed.

Digital counter output

N2 = 1000 × (100 mV / 100 mV)
   = 1000 counts

The counter shows 1000 (when Vin = Vref the de-integration takes exactly as many counts as the integration).

Conversion time

T1 = N1 × T = 1000 × 83.33 µs = 83.33 ms
T2 = N2 × T = 1000 × 83.33 µs = 83.33 ms
Tc = T1 + T2 = 83.33 + 83.33 = 166.67 ms

Answer: digital output = 1000 counts; T1 = T2 = 83.33 ms; conversion time ≈ 166.67 ms.

Note: this is also the maximum conversion time, because Vin = Vref is the full-scale input. A smaller input gives a shorter T2, while T1 stays fixed at 83.33 ms.

A non-inverted (voltage-mode) R-2R ladder DAC is built from only two resistor values, R and 2R. The digital bits switch each 2R leg between Vref (bit = 1) and ground (bit = 0). The output is taken at the MSB end of the ladder and is usually buffered by an op-amp.

Circuit (4-bit)

 Vo <--+-----R-----+-----R-----+-----R-----+
       |           |           |           |
       2R          2R          2R          2R      2R
       |           |           |           |       |
      b3(MSB)     b2          b1          b0(LSB) GND
  (each switch: 1 -> Vref, 0 -> GND)
 Vo -> non-inverting buffer -> Vout

Key property

Looking left from any node towards the LSB end, the resistance is 2R. The LSB node sees 2R (its own leg) in parallel with the 2R termination, which is R, plus the series R, which gives 2R. This repeats at every node.

Derivation by superposition

Take one bit at a time with the other switches at ground.

1. MSB (b3) alone. The rest of the ladder seen from the output node is 2R to ground. The MSB leg 2R and the 2R to ground form a divider: V = Vref/2.
2. b2 alone. At node 2 the Thevenin source is Vref/2. Moving one node towards the output, the voltage halves again: V = Vref/4.
3. In the same way b1 gives Vref/8 and b0 (LSB) gives Vref/16.

Adding the contributions:

Vo = Vref (b3/2 + b2/4 + b1/8 + b0/16)
   = (Vref / 2⁴)(8·b3 + 4·b2 + 2·b1 + b0)

For an n-bit ladder:

Vo = (Vref / 2ⁿ) · Σ bk·2ᵏ   (k = 0 … n−1)
   = Vref · D / 2ⁿ

Here D is the decimal value of the input word.

Results

• Resolution (1 LSB) = Vref/2ⁿ
• Full-scale output = Vref(2ⁿ − 1)/2ⁿ
• Output impedance of the ladder is always R, so a buffer with gain (1 + Rf/R1) can be added: Vout = (1 + Rf/R1)·Vref·D/2ⁿ.

Example: n = 4, Vref = 8 V, D = 1010 (10). Vo = 8 × 10/16 = 5 V.

Advantages

• Only two resistor values, so it is easy to trim and to make as an IC.
• The output resistance is constant at R.

Drawback: the voltage at each node changes as bits switch, so stray capacitances charge and discharge. This makes it slower than the inverted (current-mode) ladder.

A bipolar DAC gives both positive and negative output voltages. It does this by adding a fixed offset of half full scale to a normal (unipolar) ladder DAC, using offset-binary coding.

Advantages over the binary weighted resistor DAC

• It converts signed (bipolar) signals. The binary weighted DAC gives only one polarity.
• It is usually built on an R-2R ladder, so it needs only two resistor values. The binary weighted DAC needs a wide spread (R to 2ⁿ⁻¹R), which is hard to make accurately.
• It gives better accuracy and is easier to make as an IC for large n.
• Zero output sits at mid-code, so it suits AC signals, audio, and servo control that needs both directions.

Output voltage

 Vref --[R-2R ladder]--> I_D --+
                               |      Rf
 -Vref --[ R_off ]--> I_off ---+---/\/\/---+
                               |           |
                             (-)\          |
                                 >---------+--> Vo
                             (+)/
                              GND

The ladder gives a current proportional to the code: I_D = (Vref/R)(D/2ⁿ). The offset resistor draws a constant current of half full scale. With Rf chosen for a gain of 2:

Vo = Vref · (2D/2ⁿ − 1)
   = Vref · (D − 2ⁿ⁻¹) / 2ⁿ⁻¹

where D = b3·8 + b2·4 + b1·2 + b0 for a 4-bit converter. (The overall sign depends on the inverting stage; the textbook form is shown.)

Outputs for 0000, 1000 and 1111 (n = 4)

So the output swings from −Vref to almost +Vref. Code 1000 gives zero, and the MSB works as a sign bit (1 = positive, 0 = negative).

In a counter (count-up) type ADC, the counter starts from zero at START and counts clock pulses. The DAC output rises one step per pulse. The counter stops when the DAC output just exceeds Vin, because the comparator output goes LOW, which disables the AND gate and signals EOC.

Given

• n = 4 bits, VFS = 12.00 V (DAC output for 1111)
• Clock PRF = 10 kHz, so T = 1/10 kHz = 0.1 ms

i) Maximum and minimum conversion time

• Maximum: the counter may have to go through all 2ⁿ − 1 = 15 counts.

Tc(max) = (2ⁿ − 1) × T = 15 × 0.1 ms = 1.5 ms

• Minimum: one clock pulse (for a very small input).

Tc(min) = 1 × T = 0.1 ms

(Some books count 2ⁿ pulses for the maximum, giving 1.6 ms.)

ii) Resolution

With VFS taken as the output for the full code 1111:

Resolution = VFS / (2ⁿ − 1) = 12 / 15 = 0.8 V per step

In percentage terms: 1/(2⁴ − 1) = 6.67 % of full scale.

iii) Output for Vin = 4.25 V

The counter stops at the first count whose DAC voltage is greater than Vin:

N = floor(4.25 / 0.8) + 1 = 5 + 1 = 6
Tc = N × T = 6 × 0.1 ms = 0.6 ms

Answer:

• Tc(max) = 1.5 ms, Tc(min) = 0.1 ms
• Resolution = 0.8 V
• For Vin = 4.25 V: output count = 6 = 0110 (D3 D2 D1 D0), conversion time = 0.6 ms

(If resolution is instead taken as VFS/2ⁿ = 0.75 V, the count is still 6, so the output and the 0.6 ms time do not change.)

Why current-mode R-2R is preferred over voltage-mode R-2R

In the current-mode (inverted) ladder, Vref drives the ladder and each 2R leg is switched between the op-amp virtual ground and true ground. Both are at 0 V.

• Node voltages never change. Every ladder node stays at a fixed voltage whatever the input code. Stray capacitances do not charge and discharge, so settling is much faster. In the voltage-mode ladder the node voltages change with each bit.
• Constant current from Vref. The reference sees a constant load of R, so it is not disturbed and glitches are smaller.
• Switches work near ground potential. Simple MOS switches can be used, with small and equal voltage drops, which gives better accuracy.
• The branch currents are fixed binary-weighted values (I/2, I/4, …) that are simply steered. This suits high-speed IC DACs.

Bipolar DAC

A bipolar DAC adds an offset current (half of full scale) of opposite sign to the ladder current. The output then covers both negative and positive values.

 Vref -->[ current-mode R-2R ]--I_D--+
                                     |     Rf
 -Vref ---------[ 2R ]------I_os-----+--/\/\/--+
                                     |         |
                                   (-)\        |
                                       >-------+--> Vo
                                   (+)/
                                    GND

Derivation (4-bit):

1. The ladder current into the summing node:

I_D = (Vref/R)(b3/2 + b2/4 + b1/8 + b0/16) = (Vref/R)(D/16)

2. The offset current from −Vref through 2R:

I_os = −Vref / 2R

3. The op-amp gives Vo = −Rf (I_D + I_os). Take Rf = 2R:

Vo = −2R [ (Vref/R)(D/16) − Vref/(2R) ]
   = −Vref (2D/16 − 1)
   = Vref (1 − D/8)

For n bits: Vo = −Vref(2D/2ⁿ − 1). A final unity inverter, or swapping the reference signs, gives Vo = Vref(2D/2ⁿ − 1).

Justifying the name

The output takes both polarities, negative for codes below 1000 and positive above it, with zero at mid-code. Because the output is two-polarity (bipolar), it is called a bipolar DAC. A unipolar DAC gives only 0 to +FS. The code used is offset binary, where the MSB acts as the sign bit.

In a count-up (counter) type ADC, the counter increases by one per clock pulse from zero. The DAC output grows by one step each time. Conversion ends when the DAC output first exceeds Vin.

Given

• n = 4 bits, VFS = 16.00 V (DAC output for 1111)
• Minimum conversion time = 0.1 ms

a) PRF of the clock

The minimum conversion time is one clock period (the comparator trips after the first pulse):

T = Tc(min) = 0.1 ms
PRF = 1/T = 1/0.1 ms = 10 kHz

b) Resolution

Resolution = VFS / (2ⁿ − 1) = 16 / 15 = 1.067 V per step
%Resolution = 1/(2⁴ − 1) × 100 = 6.67 %

c) Digital output and conversion time for Vin = 6.25 V

The counter stops at the first count N where N × 1.067 V > 6.25 V:

N = floor(6.25 / 1.0667) + 1 = 5 + 1 = 6
Tc = N × T = 6 × 0.1 ms = 0.6 ms

Answer:

• PRF = 10 kHz
• Resolution = 1.067 V (6.67 %)
• Digital output = 0110 (decimal 6), conversion time = 0.6 ms

Maximum conversion time for reference: 15 × 0.1 = 1.5 ms.

(If a book defines resolution as VFS/2ⁿ = 1 V, the counter stops at count 7 (7 V > 6.25 V), giving 0111 and 0.7 ms. The method is the same.)

A bipolar DAC produces both positive and negative output voltages. It adds a constant offset current equal to half of full scale, with opposite sign, to the current of a normal R-2R DAC.

Circuit

 Vref -->[ R-2R ladder ]--I_D----+
                                |   Rf=2R
 -Vref -----[ 2R ]----I_os------+--/\/\/--+
                                |         |
                              (-)\        |
                                  >-------+--> Vo
                              (+)/
                               GND

Derivation

1. The R-2R ladder (current mode) sends this current into the virtual ground:

I_D = (Vref/R)(b(n−1)/2 + b(n−2)/4 + … + b0/2ⁿ)
    = (Vref/R) · D/2ⁿ

2. The offset branch from −Vref through 2R gives:

I_os = −Vref/(2R)

3. The inverting summer output with Rf = 2R:

Vo = −Rf (I_D + I_os)
   = −2R [ (Vref/R)(D/2ⁿ) − Vref/(2R) ]
   = −Vref (2D/2ⁿ − 1)

Taking the polarity after an output inverter (or reversed references), the standard bipolar (offset binary) result is:

Vo = Vref (2D/2ⁿ − 1) = Vref (D − 2ⁿ⁻¹) / 2ⁿ⁻¹

• D = 0 gives −Vref
• D = 2ⁿ⁻¹ (MSB only) gives 0
• D = 2ⁿ − 1 gives Vref(1 − 2/2ⁿ)

Step size = 2Vref/2ⁿ.

Transfer curve for 3-bit bipolar DAC (n = 3)

Vo = Vref(2D/8 − 1), step = Vref/4.

 Vo/Vref
 +0.75 |                            +---
 +0.50 |                        +---+
 +0.25 |                    +---+
  0.00 |----------------+---+-----------
 -0.25 |            +---+
 -0.50 |        +---+
 -0.75 |    +---+
 -1.00 +----+
       000 001 010 011 100 101 110 111

The staircase goes from −Vref at 000 up through zero at 100 to +0.75 Vref at 111. It is symmetric about mid-code, which shows the bipolar nature of the output.

A flash (parallel or simultaneous) ADC is the fastest type of ADC. It compares the input with all quantization levels at the same time, using 2ⁿ − 1 comparators, and a priority encoder gives the binary output in one step.

Circuit (2-bit / 3-level example)

 +Vref
   |
   R  -------(-)C3
   |  3Vref/4 (+)<-Vin -->+
   R  -------(-)C2        |
   |  2Vref/4 (+)<-Vin -->+ PRIORITY
   R  -------(-)C1        | ENCODER -> B1 B0
   |  1Vref/4 (+)<-Vin -->+
   R
   |
  GND

A 3-bit flash ADC uses 8 equal resistors and 7 comparators in the same way.

Working

1. The resistor divider makes the reference levels Vref/4, 2Vref/4 and 3Vref/4 (for n bits, steps of Vref/2ⁿ).
2. Vin goes to the + input of every comparator at the same time.
3. Each comparator whose reference is below Vin gives 1; the others give 0. The comparator outputs form a thermometer code.
4. The priority encoder converts the thermometer code into binary.

The conversion time is only one comparator delay plus the encoder delay (nanoseconds). No clock-by-clock search is needed, which is why it is called "flash".

Demerits compared with other ADCs

• Very large hardware: it needs 2ⁿ − 1 comparators and 2ⁿ resistors. An 8-bit flash needs 255 comparators, while SAR or dual slope ADCs need only one.
• High cost, power and chip area, which grow exponentially with the number of bits.
• Limited resolution in practice (usually 8 bits or less). Comparator offsets and resistor mismatch limit accuracy.
• High input capacitance, because Vin drives all comparators. This loads the source.
• It can produce sparkle codes and bubbles in the thermometer code at high speed.

A 5-bit voltage-mode R-2R ladder DAC uses resistors R and 2R only. Each bit switches its 2R leg to Vref (bit 1) or ground (bit 0). The output is taken at the MSB end of the ladder through a buffer.

Circuit

 Vo<-+----R----+----R----+----R----+----R----+
     |         |         |         |         |
     2R        2R        2R        2R        2R     2R
     |         |         |         |         |      |
    b4        b3        b2        b1        b0     GND
   (MSB)                                  (LSB)
  each switch: 1 -> Vref, 0 -> GND
  Vo -> voltage follower (op-amp) -> Vout

Output relation

Each bit adds a binary-weighted part of Vref (MSB gives Vref/2, the next Vref/4, and so on):

Vo = Vref (b4/2 + b3/4 + b2/8 + b1/16 + b0/32)
   = Vref · D / 2⁵

Calculation for input 10110, Vref = 1 V

D  = 1·16 + 0·8 + 1·4 + 1·2 + 0·1 = 22
Vo = 1 V × 22/32
   = 1 × (1/2 + 1/8 + 1/16)
   = 0.5 + 0.125 + 0.0625
   = 0.6875 V

Answer: Vo = 0.6875 V with a unity-gain buffer.

Resolution of this DAC = 1/32 = 31.25 mV. Full-scale output = 31/32 = 0.96875 V.

(If the ladder output drives an inverting amplifier of gain −1, the output is −0.6875 V. The magnitude is the same.)

A dual slope ADC is an integrating ADC. It integrates the unknown input for a fixed time, then integrates a reference of opposite polarity until the integrator output returns to zero. The time taken for the second part is proportional to the input.

Block diagram

 Vin  --o S1                 C
 -Vref--o--+--[R]--+--------||--------+
                   |                  |
                  (-)\                |
                      >---------------+--Vo1-->[COMPARATOR]
                  (+)/                              |
                   |                                v
                  GND        CLOCK-->[COUNTER]<-->[CONTROL]
                                        |
                                   digital out

Working

1. Reset: the counter is cleared and the capacitor is discharged (Vo1 = 0).
2. Integration (fixed time T1): S1 connects Vin. The integrator output ramps at a slope set by Vin/RC, while the counter counts a fixed N1 = 2ⁿ pulses. So T1 = N1·Tclk.

Vo1(T1) = −Vin·T1 / RC

3. De-integration (variable time T2): when the counter overflows, it resets and S1 switches to −Vref (opposite polarity). The output ramps back towards zero at a fixed slope Vref/RC, and the counter counts again.
4. Stop: when Vo1 reaches zero, the comparator changes state and the control logic stops the counter. Then:

Vin·T1 / RC = Vref·T2 / RC
T2 = T1·Vin / Vref,   N2 = N1·Vin / Vref

The count N2 is the digital output.

 Vo1
  |    /\          (larger Vin: steeper up-ramp)
  |   /  \
  |  /    \     same down-slope (Vref fixed)
  | /      \
  |/________\_____ t
  |<- T1 ->|<T2>|

R, C and the clock frequency cancel out, so the converter is accurate. Integration also averages out noise. It is slow (tens of ms) and used in digital voltmeters.

Integral linearity of a DAC

Integral linearity (integral non-linearity, INL) is the maximum deviation of the actual DAC transfer curve from the ideal straight line joining zero and full scale. It is measured in LSB or % of full scale, after removing offset and gain error.

• Ideal: each output level lies exactly on the straight line Vo = D × LSB.
• INL = max |Vactual(D) − Videal(D)|, for example ±½ LSB.
• It is caused by resistor mismatch and switch resistance. A small INL means the output is proportional to the code over the whole range.

A 4-bit voltage-mode R-2R ladder DAC uses only two resistor values, R and 2R. Each 2R leg is switched to Vref (bit 1) or ground (bit 0). The output is taken from the MSB end through a buffer.

Design choices

• Resistors: R = 10 kΩ, 2R = 20 kΩ (1 % metal film, matched)
• Reference: Vref = 5 V
• Switches: CMOS analog switches (for example CD4066) controlled by b3 … b0
• Output buffer: op-amp voltage follower (for example 741 or TL081) so the load does not disturb the ladder (ladder output resistance = R = 10 kΩ)

 Vo<-+---10k---+---10k---+---10k---+
     |         |         |         |
    20k       20k       20k       20k      20k
     |         |         |         |        |
    b3        b2        b1        b0       GND
  (MSB)                         (LSB)
  bit=1 -> Vref (5 V), bit=0 -> GND

  Vo --> (+) op-amp follower --> Vout = Vo

Derivation of output

Looking towards the LSB from any node, the resistance is 2R. So each node splits the current equally, and each bit's effect at the output is half that of the previous bit. By superposition:

b3 alone -> Vref/2
b2 alone -> Vref/4
b1 alone -> Vref/8
b0 alone -> Vref/16

Vo = Vref (b3/2 + b2/4 + b1/8 + b0/16)
   = Vref · D / 16      (D = 8b3 + 4b2 + 2b1 + b0)

With Vref = 5 V:

• Resolution = 5/16 = 0.3125 V
• Full scale (1111) = 5 × 15/16 = 4.6875 V
• Example: 1010 gives 5 × 10/16 = 3.125 V

For a larger output, use a non-inverting amplifier: Vout = (1 + Rf/R1)·Vref·D/16.

Unipolar vs bipolar DAC

Applications of sigma-delta ADC

A sigma-delta (ΣΔ) ADC uses oversampling, noise shaping and digital filtering. It gives very high resolution (16 to 24 bits) at low to medium speed. It is used in:

• Digital audio: CD and studio recording, codecs, mobile phones
• Precision measurement: weighing scales, strain gauges, thermocouples
• Digital voltmeters and data acquisition
• Voice-band telecommunication, modems and seismic sensors

Dual slope ADC numerical

Given: n = 8, R = 20 kΩ, C = 0.001 µF, Vin = −0.25 V, t1 = 160 µs, clock = 3.125 MHz.

1. Integrator time constant

RC = 20×10³ × 0.001×10⁻⁶ = 20×10⁻⁶ s = 20 µs

2. Maximum voltage reached during integration The inverting integrator output after t1 is:

Vo(max) = −(1/RC) ∫₀^t1 Vin dt = −Vin·t1/RC
        = −(−0.25)(160 µs)/(20 µs)
        = +2 V

So the integrator output reaches 2 V.

3. Digital output The reference voltage is not given. Assume Vref = 1 V (of opposite polarity to Vin), the usual value for this problem. During de-integration the output falls from 2 V to 0 at slope Vref/RC:

t2 = Vo(max) · RC / Vref = 2 × 20 µs / 1 = 40 µs
Clock period Tclk = 1/3.125 MHz = 0.32 µs
N = t2 / Tclk = 40 / 0.32 = 125

In binary (8 bits): 125 = 01111101.

Check with the dual slope relation: t2 = t1·|Vin|/Vref = 160 × 0.25/1 = 40 µs, which matches.

Answer: Vmax = 2 V. Digital output = 125 = 01111101₂ (taking Vref = 1 V). For any other Vref (in volts), N = 125/Vref.

A dual slope ADC converts a voltage into a time interval by integrating twice: first the input for a fixed time, then a reference until the integrator returns to zero. The second time, measured by a counter, is the digital output.

Block diagram

 Vin  --o S1                  C
 -Vref--o--+--[R]--+---------||-------+
                   |                  |
                  (-)\                |
                      >---------------+-- Vo1
                  (+)/                    |
                   |                 [COMPARATOR]
                  GND                (zero detect)
                                          |
  CLOCK --> [ n-bit COUNTER ] <--> [ CONTROL LOGIC ]
                 |                       |
            digital output         controls S1, reset

Working principle

1. Reset: the counter is cleared and C is discharged.
2. Phase 1 (fixed time T1): S1 connects Vin. The integrator ramps while the counter counts N1 = 2ⁿ fixed pulses, so T1 = N1·Tclk.

Vo1(T1) = −(1/RC) ∫₀^T1 Vin dt = −Vin·T1/RC

3. Phase 2 (variable time T2): at counter overflow S1 switches to −Vref. The output ramps back with a fixed slope Vref/RC. The counter restarts from zero.
4. When Vo1 crosses zero, the comparator stops the counter. The count N2 is the result.

 |Vo1|
   |     /\
   |    /  \           up-slope ∝ Vin
   |   /    \          down-slope ∝ Vref (fixed)
   |  /      \
   |_/________\______ t
     |<-T1 ->|<-T2->|

Proof that output is independent of RC

The charge gained in phase 1 equals the charge removed in phase 2:

Vin·T1 / RC = Vref·T2 / RC

RC is on both sides and cancels:

T2 = T1 · Vin/Vref
N2·Tclk = N1·Tclk · Vin/Vref
N2 = N1 · Vin / Vref

The result has no R, no C and not even the clock period. It depends only on Vin/Vref and the fixed count N1. Slow drift in R, C or clock frequency therefore does not cause error, as long as it stays the same during one conversion.

Why it is inherently noise immune

• The converter measures the average of Vin over T1, not an instant value: N2 ∝ (1/T1)∫Vin dt.
• Random noise has zero average, so integration removes most of it.
• If T1 is an exact multiple of the mains period (for example 20 ms for 50 Hz), any 50 Hz hum and its harmonics integrate to exactly zero:

∫₀^T1 Vm sin(2π·50t) dt = 0   when T1 = k × 20 ms

So power-line interference is rejected completely. This is why dual slope ADCs are used in digital multimeters and panel meters.

In a 4-bit voltage-mode R-2R ladder, each bit contributes a binary-weighted fraction of the logic-1 voltage at the output. The MSB gives V/2, then V/4, V/8 and V/16. Here logic 1 = +12 V and logic 0 = 0 V.

Output due to each bit

Vo = V1 (b3/2 + b2/4 + b1/8 + b0/16),   V1 = 12 V

Resolution

The resolution is the output change for 1 LSB:

Resolution = V1 / 2⁴ = 12/16 = 0.75 V

Full scale output

Full scale output is the output for input 1111:

VFS = 6 + 3 + 1.5 + 0.75 = 11.25 V
    = 12 × 15/16 = 11.25 V

Output for input 1011

Vo = 6 (b3=1) + 0 (b2=0) + 1.5 (b1=1) + 0.75 (b0=1)
   = 8.25 V
Check: 12 × 11/16 = 8.25 V

Answer: bit outputs 6 V, 3 V, 1.5 V, 0.75 V; resolution = 0.75 V; full scale = 11.25 V; output for 1011 = 8.25 V.

The successive approximation (SAR) ADC finds the digital code bit by bit using a binary search, with one comparator and a DAC. The flash (parallel) ADC compares the input with all levels at once, using 2ⁿ − 1 comparators.

Comparison

Summary

• Resolution: SAR is better. It easily gives 10 to 16 bits. Each extra bit in a flash ADC doubles the number of comparators, so flash ADCs stay at about 8 bits or less.
• Conversion time: flash is better. It converts in one step (tens of ns). SAR needs n clock cycles, which is still much faster than counter or dual slope types.
• Cost: SAR is much cheaper. Flash cost, power and area grow as 2ⁿ.

For example, an 8-bit SAR uses 1 comparator and needs 8 clocks. An 8-bit flash uses 255 comparators and converts in a single step.

An inverted (current-mode) R-2R ladder DAC applies Vref to the ladder input. The bits switch each 2R leg's current either to the op-amp's virtual ground (bit 1) or to true ground (bit 0). The op-amp converts the total current into a voltage.

Circuit (4-bit)

 Vref
  |  I     I/2       I/4       I/8
  +---R----+----R----+----R----+
  |        |         |         |
  2R       2R        2R        2R      2R
  |I/2     |I/4      |I/8      |I/16    |
  S3       S2        S1        S0      GND
 (b3)     (b2)      (b1)      (b0)
  1 -> to Iout line   0 -> to GND

  Iout line --> (-) op-amp, Rf from output to (-)
                (+) to GND        Vo = −Iout·Rf

Derivation

Both switch positions are at 0 V (virtual ground or ground), so the ladder always sees the same load. The resistance looking into the ladder from Vref is R, so:

I = Vref / R

At each node the current divides equally (2R down, 2R to the right), so the branch currents are I/2, I/4, I/8, I/16. The current reaching the op-amp:

Iout = (Vref/R)(b3/2 + b2/4 + b1/8 + b0/16)
     = (Vref/R)(D/16)

The op-amp output:

Vo = −Rf · Iout
   = −(Rf/R) · Vref (b3/2 + b2/4 + b1/8 + b0/16)
   = −(Rf/R) · Vref · D / 2⁴

With Rf = R: Vo = −Vref·D/16. For example, 1000 gives −Vref/2.

Why the inverted R-2R ladder is better

• Node voltages stay constant whatever the code, because each switch only moves current between two 0 V points. Stray capacitances do not charge and discharge, so the DAC settles fast with fewer glitches. In the non-inverted ladder the node voltages change with every bit.
• The reference source sees a constant load (R), so it stays steady.
• The switches always work at ground potential, so simple MOS switches give accurate, equal behaviour.

A dual slope integrating ADC integrates the input for a fixed time T1, then integrates a reference of opposite polarity until the output returns to zero. The time T2 taken for this is measured by a counter and is proportional to the input.

Block diagram

 Vin  --o S1                 C
 -Vref--o--+--[R]--+--------||--------+
                   |                  |
                  (-)\                |
                      >---------------+--Vo1-->[COMPARATOR]
                  (+)/                              |
                   |                                v
                  GND        CLOCK-->[COUNTER]<-->[CONTROL]
                                        |
                                   digital out

Working

1. Reset: the counter is cleared and the integrator capacitor is shorted.
2. Run-up (T1 fixed): S1 connects Vin. The integrator output becomes Vo1 = −Vin·T1/RC. T1 = 2ⁿ clock pulses, and the counter overflows at the end of T1.
3. Run-down (T2 variable): S1 connects −Vref. The output returns to zero at a fixed slope Vref/RC while the counter counts from zero.
4. End: the comparator detects zero crossing and stops the counter.

Vin·T1/RC = Vref·T2/RC
N2 = N1 · Vin/Vref

  Vo1
   |     /\      <- high Vin
   |    /  \
   |   / /\ \    <- low Vin (same down slope)
   |__/_/__\_\_____ t
      |<-T1->|T2a|
             |<-T2b->|

R, C and clock drift cancel out, and noise (including mains hum) is averaged out. It is accurate but slow, and it is used in DMMs.

Why quad slope is more accurate than dual slope

A dual slope ADC still has errors that do not cancel: integrator op-amp offset voltage, input bias current, comparator offset and delay, and switch leakage. These add a fixed error, especially near zero input.

A quad slope ADC adds a calibration (auto-zero) cycle:

• Slopes 1 and 2: the input is grounded (Vin = 0). The converter integrates and de-integrates, and the count obtained measures only the offset errors.
• Slopes 3 and 4: the normal dual slope conversion of Vin, which includes the same errors.
• The control logic subtracts the first count from the second, so the offset and bias errors cancel.

The result depends only on Vin/Vref, so the quad slope ADC gives better accuracy, especially for small inputs, at the cost of a longer conversion time.

A tracking (servo or up/down counter) ADC is an improved counter-type ADC. It uses an up/down counter in place of the up counter, so the DAC output follows (tracks) the input continuously. It does not restart from zero for each conversion.

Block diagram

 Vin -------------------(+)\
                            >-- comparator --+
        +-------------- (-)/                 | U/D
        |                                    v
        |     +------------------------------+
        |     |  n-bit UP/DOWN COUNTER       |<-CLOCK
        |     +------------------------------+
        |                  | D(n-1)..D0
        |                  v
        +--------- [ n-bit DAC ] ---> digital output
                     V_DAC

Working

1. The comparator compares Vin with the DAC output V_DAC.
2. If Vin > V_DAC: the comparator output is HIGH, the counter is set to count up, and V_DAC rises one step per clock.
3. If Vin < V_DAC: the comparator output is LOW, the counter counts down, and V_DAC falls one step per clock.
4. At the first conversion the counter climbs from zero like a simple counter ADC. After that, the counter only changes by the amount Vin has changed, so the next conversion takes just a few clock pulses.
5. When V_DAC reaches Vin, the output toggles up and down by ±1 LSB around the correct value. This is the steady-state "bit bobble". The counter contents give the digital value of Vin at any instant.

 V
  |            ____/\/\/\___      V_DAC (staircase)
  |       ____/             \__/\/\
  |   ___/    Vin (smooth) ~~~~~~~~
  |__/
  +------------------------------ t
     first lock     tracking (±1 LSB)

Features

• Fast for slowly varying signals: the conversion time after locking is a few clocks, not up to 2ⁿ.
• Continuous output, with no START pulse needed each time.
• Limitation: if Vin changes faster than 1 LSB per clock (slew limit = LSB × fclk), the counter cannot follow and the output lags.
• The ±1 LSB toggling at steady state needs a latch or display hold.
• Uses: tracking slowly changing signals in control systems, servo systems and data loggers.

Comparison with simple count-up ADC