Operational Amplifier Circuits

Essential conditions for a current mirror

A current mirror is a circuit that copies (mirrors) a reference current IREF into an output branch. It works only if:

• Matched transistors: Q1 and Q2 must have the same IS (same VBE–IC curve), same β and same Early voltage. This is easy in an IC because both are made in the same process steps, side by side.
• Same temperature: both transistors must be at the same temperature (close together on one chip), so that VBE changes track each other.
• Equal VBE: the bases are tied together and the emitters are tied together (or returned to the same rail), so VBE1 = VBE2 and therefore IC2 = IC1.
• Output transistor in the active region: Q2 must have VCE2 > VCE(sat), i.e. the load must leave enough voltage across Q2.
• High β: so that the base currents taken from the reference branch are negligible.

Output resistance of the Widlar current source

The Widlar current source is a simple mirror with a resistor RE in the emitter of the output transistor Q2. It gives a small output current (µA range) from a normal reference current.

  +VCC                 IO (from load)
    |                    |
    R                    |
    | IREF               |
    +------+             |
    |      |             |
    C1     |             C2
  Q1  B----+-------------B  Q2
    E1                   E2
    |                    |
    |                    RE
    |                    |
   GND                  GND

DC relation (neglecting base currents):

VBE1 = VBE2 + IO·RE
VT ln(IREF/IS) = VT ln(IO/IS) + IO·RE
IO·RE = VT ln(IREF/IO)

Small-signal model: Q1 is diode-connected, so its resistance is only about 1/gm1 and the base of Q2 is close to ac ground. Apply a test voltage vx at the collector of Q2 and let ix flow into it.

Emitter node: ix flows into RE ‖ rπ (rπ goes to the
grounded base), so
   ve  = ix (RE ‖ rπ) = ix R'E
Base is grounded:
   vbe = 0 - ve = -ix R'E
Current into collector:
   ix  = gm vbe + (vx - ve)/ro
       = -gm ix R'E + (vx - ix R'E)/ro
Multiply by ro and collect terms:
   vx  = ix ro + ix R'E (1 + gm ro)
   Ro  = vx/ix = ro + R'E (1 + gm ro)
Since gm ro >> 1:
   Ro ≈ ro (1 + gm R'E),   R'E = RE ‖ rπ

If RE << rπ, then Ro ≈ ro(1 + gm RE), where gm = IO/VT and ro = VA/IO. A simple mirror has Ro = ro only, so the Widlar source has an output resistance larger by the factor (1 + gm RE), which may be 5 to 20 or more. This is the result of the current-series negative feedback provided by the unbypassed RE: any rise in IO raises the drop across RE, lowers VBE2 and pulls IO back down.

A differential amplifier is a two-input amplifier that amplifies the difference between its two input voltages and rejects any signal common to both. It is the input stage of every op-amp.

          +VCC      +VCC
           |          |
           RC         RC
           |--Vo1  Vo2--|
        C1 |          | C2
  V1 --B Q1            Q2 B-- V2
         E1|          |E2
           +----+-----+
                |
           RE or current source
                |
              -VEE

Output: Vo = Ad·Vd + Acm·Vcm, where Vd = V1 − V2 (difference signal) and Vcm = (V1 + V2)/2 (common-mode signal).

Key results (BJT pair, gm = IC/VT):

• Differential gain, double-ended output: Ad = gm·RC; single-ended: gm·RC/2.
• Common-mode gain (single-ended): Acm ≈ −RC/(2RE), small when RE is large.
• CMRR = |Ad/Acm| ≈ gm·RE (single-ended). A constant-current tail (very large RE) gives very high CMRR.
• Differential input resistance Rid = 2rπ.

Configurations: dual-input balanced output, dual-input unbalanced output, single-input balanced output and single-input unbalanced output.

Features and uses: direct coupling (no capacitors, so it amplifies down to dc), good temperature stability because drifts in both halves cancel, rejection of noise and hum picked up equally by both inputs, and use as the input stage of op-amps, instrumentation amplifiers and comparators.

Benefits of the Widlar source over a simple mirror

In a simple mirror IO ≈ IREF = (VCC − VBE)/R, so a small current needs a huge resistor. The Widlar source adds RE in the emitter of Q2, giving IO·RE = VT ln(IREF/IO).

So the Widlar source gives small, stable bias currents with practical resistor values, a higher output resistance (better current source) and lower dependence on supply voltage. It is used in the input-stage biasing of the 741.

Output resistance of the Widlar current source

  +VCC                 IO (from load)
    |                    |
    R                    |
    | IREF               |
    +------+             |
    |      |             |
    C1     |             C2
  Q1  B----+-------------B  Q2
    E1                   E2
    |                    |
    |                    RE
    |                    |
   GND                  GND

Small-signal model: Q1 is diode-connected, so its resistance is only about 1/gm1 and the base of Q2 is close to ac ground. Apply a test voltage vx at the collector of Q2 and let ix flow into it.

Emitter node: ix flows into RE ‖ rπ (rπ goes to the
grounded base), so
   ve  = ix (RE ‖ rπ) = ix R'E
Base is grounded:
   vbe = 0 - ve = -ix R'E
Current into collector:
   ix  = gm vbe + (vx - ve)/ro
       = -gm ix R'E + (vx - ix R'E)/ro
Multiply by ro and collect terms:
   vx  = ix ro + ix R'E (1 + gm ro)
   Ro  = vx/ix = ro + R'E (1 + gm ro)
Since gm ro >> 1:
   Ro ≈ ro (1 + gm R'E),   R'E = RE ‖ rπ

If RE << rπ, then Ro ≈ ro(1 + gm RE), where gm = IO/VT and ro = VA/IO. A simple mirror has Ro = ro only, so the Widlar source has an output resistance larger by the factor (1 + gm RE), which may be 5 to 20 or more. This is the result of the current-series negative feedback provided by the unbypassed RE: any rise in IO raises the drop across RE, lowers VBE2 and pulls IO back down.

In an active-load differential amplifier the collector resistors RC are replaced by a PNP current mirror (Q3, Q4). We compare the single-ended output gain in both cases.

           +VCC          +VCC
            |              |
           Q3 (diode)----- Q4      PNP mirror (active load)
            |              |
            +-- i1    i4 --+---- Vo
            |              |
  V1 --B   Q1             Q2   B-- V2
            |              |
            +------+-------+
                   |
                 I (tail current source)
                   |
                 -VEE

Passive load (RC)

With a differential input vd = v1 − v2, the emitters form an ac ground and each transistor gets ±vd/2:

ic1 = +gm vd/2 ,  ic2 = -gm vd/2
Single-ended output at collector of Q2:
vo = -ic2·RC = gm·RC·vd/2
Ad(passive) = gm RC / 2

Only the signal current of Q2 reaches the output; the signal current of Q1 is wasted in its own RC.

Active load (current mirror)

1. Q1 current increases by gm·vd/2. This current flows through diode-connected Q3.
2. The mirror copies it, so i4 = ic1 = +gm vd/2 flows from Q4 into the output node.
3. Q2 current decreases by gm vd/2, so Q2 draws −gm vd/2 from the output node.
4. Net current pushed into the output node:

io = i4 - ic2 = gm vd/2 - (-gm vd/2) = gm·vd
Output node resistance = ro2 ‖ ro4
vo = gm·vd·(ro2 ‖ ro4)
Ad(active) = gm (ro2 ‖ ro4)

Comparison

If the load resistance is the same in both cases (ro2‖ro4 = RC), then

Ad(active) / Ad(passive) = gm·R / (gm·R/2) = 2

So the active load doubles the gain because the mirror transfers the signal current of Q1 to the output and both halves contribute (full differential-to-single-ended conversion). In practice ro2‖ro4 (about 50 kΩ to 100s of kΩ) is also much larger than any practical RC, so the actual gain is many times higher, e.g. gm = 40 mS and ro2‖ro4 = 50 kΩ gives Ad = 2000. The active load also takes little dc voltage and little chip area.

A current steering circuit generates one reference current on the chip and then copies ("steers") it to many points of the IC using current mirrors, so all stages are biased by constant current sources.

                 +VCC
        +---------+---------+
        |         |         |
    Q3 (diode)   Q4        Q5     PNP mirror:
        |         | I3      | I4  sources current
        |         v         v
        R       to load   to load
        |
        |       from load from load
        |         | I1      | I2
    Q1 (diode)   Q6        Q7     NPN mirror:
        |         |         |     sinks current
        +---------+---------+
                 -VEE
  (base of Q1 drives Q6, Q7; base of Q3 drives Q4, Q5)

Working:

1. A diode-connected transistor Q1 in series with resistor R sets IREF = (VCC + VEE − VBE1 − VEB3)/R (or (VCC − VBE)/R for a single mirror).
2. The VBE of Q1 is applied to the bases of several NPN transistors (Q2, …). Each copies IREF, so they sink current from the circuits connected to them.
3. The reference current also flows through a diode-connected PNP (Q3), whose VEB drives PNP transistors (Q4, Q5, …) that source current into loads.
4. Different output currents are obtained by scaling the emitter areas: I = IREF × (area of output transistor / area of reference transistor), e.g. a 2× area transistor gives 2IREF.

Advantages: only one resistor and one reference are needed; all bias currents track each other with temperature and supply; transistors are cheaper than resistors in IC area; high output resistance of current sources gives high gain and good CMRR.

Use: biasing of op-amp stages (e.g. the 741 uses one reference current for its input, gain and output stages).

Current mirror and its advantages

A current mirror is a circuit in which a reference current IREF set in one branch (through a diode-connected transistor Q1) is copied to an output branch (Q2) because both transistors have the same VBE.

  +VCC                 IO (from load)
    |                    |
    R                    |
    | IREF               |
    +------+             |
    |      |             |
    C1     |             C2
  Q1  B----+-------------B  Q2
    E1   (Q1: C tied to B)   E2
    |                    |
   GND                  GND

IREF = (VCC - VBE)/R
IREF = IC + 2IC/β  →  IO = IC = IREF/(1 + 2/β) ≈ IREF

Advantages:

• Gives a constant current that does not depend on the load (high output resistance ro).
• Uses transistors instead of large resistors, saving chip area in ICs.
• One reference can bias many stages (current steering).
• Good temperature tracking because the matched transistors are on the same chip.
• Used as an active load, giving very high gain in differential amplifiers.
• No coupling or bypass capacitors needed; works down to dc.

Output resistance of the Widlar current source

  +VCC                 IO (from load)
    |                    |
    R                    |
    | IREF               |
    +------+             |
    |      |             |
    C1     |             C2
  Q1  B----+-------------B  Q2
    E1                   E2
    |                    |
    |                    RE
    |                    |
   GND                  GND

The emitter resistor RE makes IO much smaller than IREF: IO·RE = VT ln(IREF/IO).

Small-signal model: Q1 is diode-connected, so its resistance is only about 1/gm1 and the base of Q2 is close to ac ground. Apply a test voltage vx at the collector of Q2 and let ix flow into it.

Emitter node: ix flows into RE ‖ rπ (rπ goes to the
grounded base), so
   ve  = ix (RE ‖ rπ) = ix R'E
Base is grounded:
   vbe = 0 - ve = -ix R'E
Current into collector:
   ix  = gm vbe + (vx - ve)/ro
       = -gm ix R'E + (vx - ix R'E)/ro
Multiply by ro and collect terms:
   vx  = ix ro + ix R'E (1 + gm ro)
   Ro  = vx/ix = ro + R'E (1 + gm ro)
Since gm ro >> 1:
   Ro ≈ ro (1 + gm R'E),   R'E = RE ‖ rπ

If RE << rπ, then Ro ≈ ro(1 + gm RE), where gm = IO/VT and ro = VA/IO. A simple mirror has Ro = ro only, so the Widlar source has an output resistance larger by the factor (1 + gm RE), which may be 5 to 20 or more. This is the result of the current-series negative feedback provided by the unbypassed RE: any rise in IO raises the drop across RE, lowers VBE2 and pulls IO back down.

Basic requirements of current mirror circuits

• Matched transistors: Q1 and Q2 must have the same IS (same VBE–IC curve), same β and same Early voltage. This is easy in an IC because both are made in the same process steps, side by side.
• Same temperature: both transistors must be at the same temperature (close together on one chip), so that VBE changes track each other.
• Equal VBE: the bases are tied together and the emitters are tied together (or returned to the same rail), so VBE1 = VBE2 and therefore IC2 = IC1.
• Output transistor in the active region: Q2 must have VCE2 > VCE(sat), i.e. the load must leave enough voltage across Q2.
• High β: so that the base currents taken from the reference branch are negligible.

Output resistance of the Widlar current source

  +VCC                 IO (from load)
    |                    |
    R                    |
    | IREF               |
    +------+             |
    |      |             |
    C1     |             C2
  Q1  B----+-------------B  Q2
    E1                   E2
    |                    |
    |                    RE
    |                    |
   GND                  GND

DC design relation: IO·RE = VT ln(IREF/IO).

Small-signal model: Q1 is diode-connected, so its resistance is only about 1/gm1 and the base of Q2 is close to ac ground. Apply a test voltage vx at the collector of Q2 and let ix flow into it.

Emitter node: ix flows into RE ‖ rπ (rπ goes to the
grounded base), so
   ve  = ix (RE ‖ rπ) = ix R'E
Base is grounded:
   vbe = 0 - ve = -ix R'E
Current into collector:
   ix  = gm vbe + (vx - ve)/ro
       = -gm ix R'E + (vx - ix R'E)/ro
Multiply by ro and collect terms:
   vx  = ix ro + ix R'E (1 + gm ro)
   Ro  = vx/ix = ro + R'E (1 + gm ro)
Since gm ro >> 1:
   Ro ≈ ro (1 + gm R'E),   R'E = RE ‖ rπ

If RE << rπ, then Ro ≈ ro(1 + gm RE), where gm = IO/VT and ro = VA/IO. A simple mirror has Ro = ro only, so the Widlar source has an output resistance larger by the factor (1 + gm RE), which may be 5 to 20 or more. This is the result of the current-series negative feedback provided by the unbypassed RE: any rise in IO raises the drop across RE, lowers VBE2 and pulls IO back down.

Best current source

Among the common sources, the Wilson current source (and the cascode mirror) is usually the best:

• Its output resistance is about β·ro/2, much higher than ro (simple mirror) and ro(1 + gm RE) (Widlar).
• Its β error is very small: IO = IREF[1 − 2/(β² + 2β + 2)], compared with IREF/(1 + 2/β) in the simple mirror.

Between the two derived here, the Widlar source is better than the simple mirror because it gives a higher output resistance and small currents with small resistors.

Why IO is not exactly equal to IREF

In a simple two-transistor mirror the output current IO is not exactly IREF because:

1. Finite β (base current): IREF must supply IC1 plus both base currents: IREF = IC + 2IC/β, so IO = IREF/(1 + 2/β). For β = 100, IO is about 2% less than IREF.
2. Early effect (finite ro): VCE1 = VBE ≈ 0.7 V but VCE2 is set by the load and is usually larger. Because of base-width modulation, IO = IC1(1 + (VCE2 − VBE)/VA), so IO is slightly larger and changes with output voltage.
3. Mismatch: small differences in IS (emitter area, doping) and temperature between Q1 and Q2 make VBE1 = VBE2 give unequal currents.

Output resistance of the Widlar current source

  +VCC                 IO (from load)
    |                    |
    R                    |
    | IREF               |
    +------+             |
    |      |             |
    C1     |             C2
  Q1  B----+-------------B  Q2
    E1                   E2
    |                    |
    |                    RE
    |                    |
   GND                  GND

DC relation: VBE1 − VBE2 = IO·RE, so IO·RE = VT ln(IREF/IO), giving IO << IREF.

Small-signal model: Q1 is diode-connected, so its resistance is only about 1/gm1 and the base of Q2 is close to ac ground. Apply a test voltage vx at the collector of Q2 and let ix flow into it.

Emitter node: ix flows into RE ‖ rπ (rπ goes to the
grounded base), so
   ve  = ix (RE ‖ rπ) = ix R'E
Base is grounded:
   vbe = 0 - ve = -ix R'E
Current into collector:
   ix  = gm vbe + (vx - ve)/ro
       = -gm ix R'E + (vx - ix R'E)/ro
Multiply by ro and collect terms:
   vx  = ix ro + ix R'E (1 + gm ro)
   Ro  = vx/ix = ro + R'E (1 + gm ro)
Since gm ro >> 1:
   Ro ≈ ro (1 + gm R'E),   R'E = RE ‖ rπ

If RE << rπ, then Ro ≈ ro(1 + gm RE), where gm = IO/VT and ro = VA/IO. A simple mirror has Ro = ro only, so the Widlar source has an output resistance larger by the factor (1 + gm RE), which may be 5 to 20 or more. This is the result of the current-series negative feedback provided by the unbypassed RE: any rise in IO raises the drop across RE, lowers VBE2 and pulls IO back down.

Basic requirements for a current mirror

• Matched transistors: Q1 and Q2 must have the same IS (same VBE–IC curve), same β and same Early voltage. This is easy in an IC because both are made in the same process steps, side by side.
• Same temperature: both transistors must be at the same temperature (close together on one chip), so that VBE changes track each other.
• Equal VBE: the bases are tied together and the emitters are tied together (or returned to the same rail), so VBE1 = VBE2 and therefore IC2 = IC1.
• Output transistor in the active region: Q2 must have VCE2 > VCE(sat), i.e. the load must leave enough voltage across Q2.
• High β: so that the base currents taken from the reference branch are negligible.

Why the output current is not exactly equal to IREF

• Finite β: IREF supplies IC1 plus both base currents, so IO = IREF/(1 + 2/β), slightly less than IREF.
• Early effect: VCE2 is larger than VCE1 = VBE, so IO = IC1(1 + (VCE2 − VBE)/VA), slightly more than IC1 and dependent on the load voltage.
• Mismatch in IS (area, doping) and temperature between Q1 and Q2.

Emitter resistance for the Widlar source

Given IREF = 1 mA, IO = 10 µA. Take VT = 26 mV (room temperature, about 27 °C) and neglect base currents.

  +VCC                 IO (from load)
    |                    |
    R                    |
    | IREF               |
    +------+             |
    |      |             |
    C1     |             C2
  Q1  B----+-------------B  Q2
    E1                   E2
    |                    |
    |                    RE
    |                    |
   GND                  GND

VBE1 - VBE2 = IO·RE
VT ln(IREF/IS) - VT ln(IO/IS) = IO·RE
RE = (VT/IO) · ln(IREF/IO)
   = (0.026 / 10×10⁻⁶) · ln(1 mA / 10 µA)
   = 2600 × ln(100)
   = 2600 × 4.6052
   = 11 973 Ω

Answer: RE ≈ 11.97 kΩ (about 12 kΩ). If VT = 25 mV is used, RE = 2500 × 4.6052 ≈ 11.51 kΩ. A simple mirror would need a resistor of about 1.4 MΩ (for VCC = 15 V) for the same 10 µA.

Reasons IO ≠ IREF in a simple current mirror

In a simple two-transistor mirror the output current IO is not exactly IREF because:

1. Finite β (base current): IREF must supply IC1 plus both base currents: IREF = IC + 2IC/β, so IO = IREF/(1 + 2/β). For β = 100, IO is about 2% less than IREF.
2. Early effect (finite ro): VCE1 = VBE ≈ 0.7 V but VCE2 is set by the load and is usually larger. Because of base-width modulation, IO = IC1(1 + (VCE2 − VBE)/VA), so IO is slightly larger and changes with output voltage.
3. Mismatch: small differences in IS (emitter area, doping) and temperature between Q1 and Q2 make VBE1 = VBE2 give unequal currents.

Gain of differential amplifier: active load vs passive load

Consider a BJT differential pair Q1–Q2 with tail current I, gm = (I/2)/VT. A differential input vd = v1 − v2 gives each transistor ±vd/2, so

ic1 = +gm·vd/2 ,   ic2 = -gm·vd/2

Passive load (RC in each collector), single-ended output at Q2:

vo = -ic2·RC = gm·RC·vd/2
Ad(passive) = gm·RC/2

The signal current of Q1 is lost in its own RC.

Active load (PNP current mirror Q3–Q4):

      +VCC ---- Q3(diode) ==== Q4 ---- +VCC
                  |             |
                  | ic1         +----- vo
                  |             |
       v1 ---B   Q1            Q2   B--- v2
                  +------+------+
                         I
                       -VEE

Q3 carries ic1, and the mirror copies it into Q4, so Q4 pushes ic1 = +gm vd/2 into the output node while Q2 draws ic2 = −gm vd/2 from it:

io = ic1 - ic2 = gm·vd/2 + gm·vd/2 = gm·vd
vo = gm·vd·(ro2 ‖ ro4)
Ad(active) = gm·(ro2 ‖ ro4)

For the same load resistance R (ro2‖ro4 = RC = R):

Ad(active)/Ad(passive) = gm·R / (gm·R/2) = 2

So the active load doubles the gain, because both halves of the signal current reach the output. Since ro2‖ro4 is also much larger than a practical RC, the real gain is many times higher.

Current mirror circuit

A current mirror copies a reference current to an output branch using two matched transistors with equal VBE. Q1 is diode-connected (collector shorted to base).

  +VCC                 IO (from load)
    |                    |
    R                    |
    | IREF               |
    +------+             |
    |      |             |
    C1     |             C2
  Q1  B----+-------------B  Q2
    E1   (Q1: C tied to B)   E2
    |                    |
   GND                  GND

Expression for output current

Q1 and Q2 are matched and have the same VBE, so IC1 = IC2 = IC and IB1 = IB2 = IC/β.

IREF = (VCC - VBE)/R
KCL at the collector of Q1:
IREF = IC1 + IB1 + IB2 = IC + 2IC/β
IO   = IC2 = IREF / (1 + 2/β) = IREF·β/(β + 2)

For β → ∞, IO = IREF = (VCC − VBE)/R.

Effect of finite β

Part of IREF is used to supply the base currents of both transistors, so IO is smaller than IREF:

Error = (IREF - IO)/IREF = 2/(β + 2)
β = 100  → IO = 0.980 IREF (2% error)
β = 50   → IO = 0.962 IREF (3.8% error)

The error also changes with temperature because β does. It is reduced by a buffered mirror (emitter-follower Q3 supplies the base currents, IO = IREF/(1 + 2/β²)) or a Wilson mirror.

Effect of finite output resistance

Because of the Early effect, IC2 depends on VCE2. Q1 has VCE1 = VBE, but VCE2 is set by the load:

IO = IREF/(1 + 2/β) · [1 + (VCE2 - VBE)/VA]
Output resistance  Ro = ΔVCE2/ΔIO = ro = VA/IO

So IO is not constant; it rises as the output voltage rises, and the source is not ideal (ideal Ro = ∞). For VA = 100 V and IO = 1 mA, ro = 100 kΩ, so a 10 V change in VCE2 changes IO by about 10%. Widlar, cascode and Wilson sources raise Ro to reduce this effect.

Why active load is preferred over passive load

• Much higher gain: gain = gm × load resistance. A transistor current source gives a small-signal resistance ro (50 kΩ to MΩ) while dropping only a few tenths of a volt dc. A resistor of the same value would need a very large dc drop and supply voltage.
• Gain is doubled in a differential pair: the current-mirror load converts the differential output to single-ended without losing half the signal (Ad = gm(ro2‖ro4) instead of gm·RC/2).
• Less chip area: a transistor occupies much less area than a large resistor.
• Large output swing and better use of a low supply, since the dc drop is small.
• Better CMRR and good temperature tracking (matched devices).

Advantage of Widlar current source in IC biasing

• Gives very small bias currents (µA) with small resistors: IO·RE = VT ln(IREF/IO), so a 10 µA source needs only about 12 kΩ instead of about 1.4 MΩ, saving chip area.
• Higher output resistance, Ro ≈ ro(1 + gm RE), so the current is more constant.
• The output current is less sensitive to supply voltage and β changes because of the emitter degeneration.
• Used for the low input-stage current of the 741, giving low input bias current and high input resistance.

Principle of biasing in IC design

• Large resistors and capacitors are costly in chip area, but transistors are cheap and well matched.
• So stages are direct coupled and biased with constant current sources (current mirrors) instead of resistor networks.
• A single reference current is set by one resistor and copied to all stages (current steering); scaled emitter areas or Widlar sources give other current values.

Advantages of the Widlar current source

• Small currents (µA) with small resistors, so less chip area.
• High output resistance, Ro ≈ ro(1 + gm RE).
• Lower sensitivity of IO to VCC, β and temperature.

Differential-mode voltage gain of BJT differential amplifier

         +VCC           +VCC
          |               |
          RC              RC
          +-- vo1   vo2 --+
          |               |
 v1 ---B Q1              Q2 B--- v2
          |               |
          +-------+-------+
                  | E
                  RE  (tail)
                  |
                -VEE

Apply a pure differential input: v1 = +vd/2, v2 = −vd/2. The emitter currents of Q1 and Q2 change by equal and opposite amounts, so the current in RE does not change and the common emitter point is at ac ground. Each half is then a common-emitter amplifier:

Half circuit: input vd/2, load RC, emitter grounded
ic1 = gm·(vd/2),   ic2 = -gm·(vd/2)
vo1 = -gm·RC·vd/2
vo2 = +gm·RC·vd/2

Gains (with gm = IC/VT = (IEE/2)/VT):

Double-ended output: vod = vo2 - vo1 = gm·RC·vd
   Ad = vod/vd = gm·RC = β·RC/rπ
Single-ended output:
   Ad = vo2/vd = gm·RC/2

If an unbypassed emitter resistor re' is in each emitter, Ad = RC/(re + re'). Differential input resistance = 2rπ.

In discrete circuits transistors are biased with resistor divider networks and bypass/coupling capacitors. In ICs this is not practical, so a different principle is used:

• Resistors take large chip area (a 1 MΩ resistor needs far more area than a transistor) and have poor absolute tolerance (±20%), but ratios and matching of devices are very good.
• Capacitors larger than a few tens of pF cannot be made, so coupling and bypass capacitors are not possible; stages are direct coupled.
• Transistors are cheap, small and very well matched because they are made side by side in the same process and are at the same temperature.

So IC bias circuits use constant current sources made from transistors (current mirrors). One reference current is set by a single resistor and a diode-connected transistor, and is copied to all stages by current mirrors (current steering), often with Widlar sources for small currents. The current sources also act as high-resistance active loads and tail sources, giving high gain and high CMRR, and their currents track temperature and supply changes together.

A differential amplifier amplifies the difference vd = v1 − v2 and rejects the common-mode signal vcm = (v1 + v2)/2. Its ac analysis is done by splitting any input into these two parts and using the half-circuit method.

         +VCC           +VCC
          |               |
          RC              RC
          +-- vo1   vo2 --+
          |               |
 v1 ---B Q1              Q2 B--- v2
          |               |
          +-------+-------+
                  | E
                  RE  (tail)
                  |
                -VEE

Differential-mode analysis

For v1 = +vd/2 and v2 = −vd/2, the change in IE1 equals minus the change in IE2, so the current through RE stays constant and the emitter node is ac ground.

Half circuit (CE stage, emitter grounded):
  ic1 = gm·vd/2 ,  ic2 = -gm·vd/2
  vo1 = -gm·RC·vd/2 ,  vo2 = +gm·RC·vd/2
Double-ended: Ad = (vo2 - vo1)/vd = gm·RC
Single-ended: Ad = gm·RC/2
Differential input resistance: Rid = 2rπ

Common-mode analysis

For v1 = v2 = vcm, both emitter currents change together, so the current in RE is doubled. Each half sees an emitter resistance of 2RE.

Half circuit: CE stage with 2RE in the emitter
  Acm = vo1/vcm = -gm·RC / (1 + 2gm·RE) ≈ -RC/(2RE)
Common-mode input resistance ≈ β·(2RE) per side
Double-ended output: vo2 - vo1 = 0 (ideally Acm = 0)

CMRR and total output

Single-ended:
CMRR = |Ad/Acm| = (gm·RC/2)/(RC/2RE) ≈ gm·RE
CMRR(dB) = 20 log10 |Ad/Acm|
vo = Ad·vd + Acm·vcm

For a high CMRR, RE should be very large; this is why the tail resistor is replaced by a constant current source (current mirror), whose output resistance is hundreds of kΩ. Using double-ended output with matched halves also cancels the common-mode output.

A differential amplifier with active load uses a current mirror (usually PNP, Q3–Q4) in place of the two collector resistors of the differential pair Q1–Q2.

      +VCC ---- Q3(diode) ==== Q4 ---- +VCC
                  |             |
                  |             +----- vo
       v1 ---B   Q1            Q2   B--- v2
                  +------+------+
                         I (tail source)
                       -VEE

Working: for a differential input vd, ic1 = +gm vd/2 and ic2 = −gm vd/2. Q3 carries ic1 and the mirror copies it into Q4, so the net current into the output node is ic1 − ic2 = gm·vd.

Ad = gm (ro2 ‖ ro4)   (single-ended output)
Compare passive load: Ad = gm·RC/2

Advantages:

• Gain is twice that of a passive load of equal resistance, and in practice much higher since ro2‖ro4 is large (gain of 1000 or more in one stage).
• Differential to single-ended conversion without losing half the signal.
• Small dc voltage drop and small chip area.
• Good CMRR, since a common-mode change gives equal currents that the mirror cancels at the output.

Limitations: the high output resistance must be followed by a high-input-resistance stage (e.g. Darlington or emitter follower), and the gain depends on ro, which varies with devices. It is used as the input stage of the 741 and most op-amps.

Circuit: V1 (through R1) and V3 (through R3) to the inverting input, R4 from output to inverting input, V2 through R2 to the non-inverting input with R5 to ground. Ideal op-amp assumed.

              R4
      +-----/\/\/-----+
 V1 --R1--+            |
 V3 --R3--+---(-)      |
                 >-----+---- V0
 V2 --R2--+---(+)
          |
          R5
          |
         GND

(i) Coefficients a1, a2, a3

Non-inverting input voltage (voltage divider, no input current):

V+ = V2·R5/(R2 + R5)

KCL at the inverting input, with V− = V+ = Vp:

(V1 - Vp)/R1 + (V3 - Vp)/R3 + (V0 - Vp)/R4 = 0
V0 = -(R4/R1)V1 - (R4/R3)V3 + Vp(1 + R4/R1 + R4/R3)

Substituting Vp:

a1 = -R4/R1
a3 = -R4/R3
a2 = (1 + R4/R1 + R4/R3) · R5/(R2 + R5)
   = [1 + R4/(R1 ‖ R3)] · R5/(R2 + R5)

So V0 = −(R4/R1)V1 + [1 + R4/(R1‖R3)]·[R5/(R2 + R5)]·V2 − (R4/R3)V3.

(ii) R4 short-circuited (R4 = 0)

Then a1 = a3 = 0 and a2 = R5/(R2 + R5). The output is tied directly to the inverting input and the circuit is a voltage follower of V+:

V0 = V2·R5/(R2 + R5)

V1 and V3 have no effect (the op-amp output supplies their currents).

(iii) R4 removed (R4 = ∞)

There is no feedback, so the op-amp works open-loop as a comparator with gain A (very large):

V- = (V1·R3 + V3·R1)/(R1 + R3)
V+ = V2·R5/(R2 + R5)
V0 = +Vsat  if V+ > V-
V0 = -Vsat  if V+ < V-

The output saturates near the supply rails (about ±13 V for ±15 V supply); the linear relation V0 = a1v1 + a2v2 + a3v3 no longer holds.