Operational Amplifier Characterization

Slew rate

Slew rate (SR) is the maximum rate of change of the output voltage of an op-amp, SR = (dVo/dt)max, in V/µs. It is limited by the current available to charge the internal compensation capacitor (SR = I/C).

Checking for distortion

Given: Rf = 470 kΩ, R1 = 10 kΩ, vin = 0.1 sin(200000t) V, SR = 0.5 V/µs.

Closed-loop gain |Av| = Rf/R1 = 470/10 = 47
Output peak     Vm   = 47 × 0.1 = 4.7 V
Angular freq    ω    = 2 × 10⁵ rad/s
Frequency       f    = ω/2π = 31.83 kHz
vo = -4.7 sin(ωt)
Max slope of output = ω·Vm
   = 2 × 10⁵ × 4.7 = 0.94 × 10⁶ V/s = 0.94 V/µs

Required rate 0.94 V/µs > SR 0.5 V/µs, so the output will be distorted (the sine wave turns into a triangular-like wave of smaller amplitude).

Equivalently, the full-power bandwidth for 4.7 V peak is fmax = SR/(2πVm) = 0.5 × 10⁶/(2π × 4.7) = 16.93 kHz, which is below the signal frequency of 31.83 kHz.

Remedies

Any one of the following:

1. Use an op-amp with higher slew rate: SR ≥ 0.94 V/µs (e.g. LF351 with 13 V/µs).
2. Reduce the gain: the largest undistorted output peak is Vm = SR/ω = 0.5 × 10⁶ / 2 × 10⁵ = 2.5 V, so gain ≤ 2.5/0.1 = 25. With R1 = 10 kΩ, Rf ≤ 250 kΩ.
3. Reduce the input amplitude: for gain 47, Vin(peak) ≤ 2.5/47 = 0.0532 V (53.2 mV).
4. Reduce the signal frequency below 16.93 kHz (if the application allows).

Answer: required 0.94 V/µs > 0.5 V/µs, so the output is distorted; use Rf ≤ 250 kΩ or an op-amp with SR ≥ 0.94 V/µs.

Given: inverting amplifier, R1 = 1 kΩ, Rf = 33 kΩ, f = 1 kHz, SR = 0.6 V/µs.

Closed-loop gain |Av| = Rf/R1 = 33
Output: vo = -33 Vp sin(2πft),  peak Vm = 33 Vp

(i) Maximum Vp for undistorted output

For a sine wave the maximum slope of the output is 2πf·Vm. To avoid slew-rate distortion:

2πf·Vm ≤ SR
Vm(max) = SR/(2πf)
        = 0.6 × 10⁶ / (2π × 1000)
        = 95.49 V
Vp(max) = Vm/33 = 95.49/33 = 2.894 V

Answer: Vp ≤ 2.894 V (about 2.89 V) as far as slew rate is concerned.

Note: with a ±15 V supply the output cannot exceed about ±13 V anyway, so in practice clipping (saturation) limits Vp to about 13/33 ≈ 0.39 V before the slew-rate limit is reached.

(ii) Vp = 5 V: remedies

With Vp = 5 V, Vm = 33 × 5 = 165 V and the required rate is 2π × 1000 × 165 = 1.037 V/µs > 0.6 V/µs, so the output is distorted. Two remedies:

1. Reduce the closed-loop gain: gain ≤ 95.49/5 = 19.1, i.e. Rf ≤ 19.1 kΩ (with R1 = 1 kΩ); in practice the gain must also be small enough to keep the output within the supply (e.g. gain ≤ 2.6 for ±13 V swing, Rf ≤ 2.6 kΩ).
2. Use an op-amp with a higher slew rate: SR ≥ 1.037 V/µs (e.g. LF351, 13 V/µs).

Other options: reduce the input amplitude (attenuate before the amplifier) or reduce the frequency.

Relationship between gain and bandwidth

The open-loop gain of an op-amp is very high (about 2 × 10⁵ for the 741) only at low frequencies. Because of the internal compensation capacitor it falls at −20 dB/decade above a low break frequency fo (about 5 Hz), reaching unity at ft (about 1 MHz). When negative feedback reduces the gain, the bandwidth increases by the same factor. So gain and bandwidth are inversely proportional, and their product is constant.

Gain (dB)
 106 |-------.        open loop
     |        \
  40 |---------\---.  closed loop, gain 100
     |          \  :
   0 +-----------\-:-----------> f (log)
          fo      fF  ft = 1 MHz

Proof that GBP is constant

The open-loop gain of an internally compensated op-amp (e.g. 741) has a single dominant pole at fo:

A(f) = A0 / (1 + j f/fo)
A0 = dc open-loop gain,  fo = open-loop break frequency

Apply negative feedback with feedback factor β (for a non-inverting amplifier β = R1/(R1 + Rf)):

Af(f) = A(f) / (1 + β A(f))
      = [A0/(1 + jf/fo)] / [1 + βA0/(1 + jf/fo)]
      = A0 / (1 + βA0 + jf/fo)
      = [A0/(1 + βA0)] / [1 + j f / (fo(1 + βA0))]

This is again a single-pole response, with

Closed-loop dc gain : Af0 = A0 / (1 + βA0)
Closed-loop BW      : fF  = fo (1 + βA0)
Product             : Af0 × fF = A0 × fo = constant

The factor (1 + βA0) that divides the gain multiplies the bandwidth, so gain × bandwidth = A0·fo = ft, the unity-gain bandwidth, which is fixed for a given op-amp. For the 741, A0 ≈ 2 × 10⁵ and fo ≈ 5 Hz, so GBP ≈ 1 MHz: with a gain of 10 the bandwidth is 100 kHz, with a gain of 100 it is 10 kHz.

Input offset voltage

Input offset voltage (Vio) is the dc differential voltage that must be applied between the two input terminals to make the output zero when both inputs are grounded. It arises from mismatch of the input transistors (VBE). For the 741, Vio ≈ 1 mV typical, 6 mV maximum.

Input offset current

Input offset current (Ios) is the difference between the bias currents flowing into the two inputs when the output is zero: Ios = |IB1 − IB2|. For the 741, Ios ≈ 20 nA typical, 200 nA maximum. (Input bias current IB = (IB1 + IB2)/2.)

Compensating the effect of input bias currents

The input transistors need base currents IB1 and IB2. These flow through the external resistors and produce an output voltage even with zero input.

                 Rf
          +----/\/\/----+
          |             |
 Vi --R1--+--> IB1 -(-) |
                     >--+---- Vo
     +-----> IB2 ---(+)
     |
   Rcomp
     |
    GND

Take Vi = 0 (only bias currents act). IB1 flows into the inverting input and IB2 into the non-inverting input.

Without compensation (Rcomp = 0): the non-inverting input is at 0 V, so the inverting input is also at 0 V (virtual ground). No current flows in R1, so all of IB1 comes through Rf:

Vo = IB1 · Rf

e.g. IB = 500 nA, Rf = 1 MΩ gives 0.5 V of output error with no input.

With compensation resistor Rcomp at the non-inverting input:

V+ = -IB2·Rcomp = V-
KCL at inverting node:
  (0 - V-)/R1 + (Vo - V-)/Rf = IB1
  Vo = IB1·Rf + V-(1 + Rf/R1)
     = IB1·Rf - IB2·Rcomp(1 + Rf/R1)
Choose Rcomp(1 + Rf/R1) = Rf, i.e.
  Rcomp = R1·Rf/(R1 + Rf) = R1 ‖ Rf
Then
  Vo = Rf (IB1 - IB2) = Rf · Ios

Since Ios is typically 5 to 10 times smaller than IB, the error falls a lot. The rule is: both inputs should see the same dc resistance to ground.

Other ways to reduce the effect of bias currents:

• Use op-amps with low IB (FET-input or super-β types, e.g. LF351, CA3140 with IB in pA).
• Keep Rf (and all resistors) low, since the error is IB·Rf or Ios·Rf.
• Use a T-network feedback to get high gain with smaller resistors.
• Use the offset-null terminals (pins 1 and 5 on the 741 with a 10 kΩ pot) or an external balancing network to trim the remaining output offset to zero.
• For ac amplifiers, use capacitor coupling so the dc gain is 1.

Given: SR = 1 V/µs, gain = 40 dB, input = 100 mV peak, f = 20 kHz.

Gain: 20 log10 Av = 40 dB  →  Av = 10^(40/20) = 100
Output peak: Vm = 100 × 0.1 = 10 V
Required slope of output (sine wave):
  (dVo/dt)max = 2πf·Vm
              = 2π × 20 000 × 10
              = 1.2566 × 10⁶ V/s = 1.257 V/µs

Since 1.257 V/µs > SR = 1 V/µs, the output will be distorted by slew-rate limiting (the peaks are rounded into a triangular shape and the amplitude falls).

Check with full-power bandwidth: fmax = SR/(2πVm) = 10⁶/(2π × 10) = 15.92 kHz < 20 kHz, confirming distortion.

Remedies

1. Use a faster op-amp: SR ≥ 1.257 V/µs (for margin, 2 V/µs or more, e.g. LF351 with 13 V/µs).
2. Reduce the gain: the largest undistorted output at 20 kHz is Vm = SR/(2πf) = 10⁶/(2π × 20 000) = 7.96 V, so gain ≤ 7.96/0.1 = 79.6 (about 38 dB). For example, with R1 = 1 kΩ use Rf ≤ 79.6 kΩ (standard 75 kΩ).
3. Reduce the input amplitude: at gain 100, Vin(peak) ≤ 7.96/100 = 79.6 mV.
4. Operate below 15.92 kHz if the signal frequency can be lowered.

Answer: output is distorted (needs 1.257 V/µs > 1 V/µs); use SR ≥ 1.26 V/µs or gain ≤ 79.6.

Effect of input offset voltage

Input offset voltage (Vio) is the small dc voltage that must be applied between the inputs to make the output zero. It is caused by mismatch of the input transistors (VBE and β). Its effect can be modelled as a dc source Vio in series with the non-inverting input of an ideal op-amp.

            Rf
      +---/\/\/---+
      |            |
 GND -R1--+--(-)   |
          |     >--+---- Voo
 GND --[Vio]--(+)

With the signal input grounded, the circuit is a non-inverting amplifier for Vio:

Voo = (1 + Rf/R1) · Vio

So the offset is amplified by the noise gain (1 + Rf/R1), the same for inverting and non-inverting configurations. Example: Vio = 6 mV, R1 = 1 kΩ, Rf = 100 kΩ gives Voo = 101 × 6 mV = 0.606 V at the output with no input. In open loop (comparator) even 1 mV can drive the output into saturation.

Minimizing the offset

• Offset null terminals: for the 741, a 10 kΩ potentiometer between pins 1 and 5 with the wiper to −VEE is adjusted for zero output.
• External balancing (compensating) network: a small adjustable voltage from a potentiometer across ±V, divided down, applied to the free input.
• Use low-offset op-amps (e.g. OP07, Vio ≈ 25 µV) or chopper-stabilized op-amps.
• Reduce dc gain: use the lowest gain needed; in ac amplifiers use a capacitor in series with R1 so the dc gain is 1.
• Keep the op-amp at a stable temperature, since Vio drifts (µV/°C).

Power supply rejection ratio (PSRR)

PSRR (also called supply voltage rejection ratio, SVRR) is the change in input offset voltage per unit change in supply voltage, with the other supply constant:

PSRR = ΔVio / ΔV    (µV/V)
PSRR(dB) = 20 log10 (ΔV / ΔVio)

For the 741, PSRR = 30 µV/V typical (150 µV/V max). A smaller value in µV/V (or a larger value in dB) is better.

Slew rate

Slew rate (SR) is the maximum rate of change of output voltage per unit time that an op-amp can produce, SR = (dVo/dt)max, usually in V/µs (0.5 V/µs for the 741).

Cause: inside the op-amp, a limited current Imax charges the compensation capacitor C (30 pF in the 741). Since i = C·dv/dt:

SR = (dVo/dt)max = Imax / C
741: SR = 15 µA / 30 pF = 0.5 V/µs

Slew rate and sine waves: for vo = Vm sin(2πft),

dvo/dt = 2πf·Vm·cos(2πft)
(dvo/dt)max = 2πf·Vm
No distortion if  2πf·Vm ≤ SR
Full-power bandwidth: fmax = SR / (2π·Vm)
Maximum output peak:  Vm   = SR / (2πf)

If the required rate is larger than SR, the output becomes a triangular wave with smaller amplitude (slew-rate distortion). Example: 741 at 10 V peak gives fmax = 0.5 × 10⁶/(2π × 10) ≈ 7.96 kHz. For a step input the output rises as a ramp of slope SR, e.g. a 10 V step takes 20 µs.

Proof that gain-bandwidth product is constant

The open-loop gain of an internally compensated op-amp (e.g. 741) has a single dominant pole at fo:

A(f) = A0 / (1 + j f/fo)
A0 = dc open-loop gain,  fo = open-loop break frequency

Apply negative feedback with feedback factor β (for a non-inverting amplifier β = R1/(R1 + Rf)):

Af(f) = A(f) / (1 + β A(f))
      = [A0/(1 + jf/fo)] / [1 + βA0/(1 + jf/fo)]
      = A0 / (1 + βA0 + jf/fo)
      = [A0/(1 + βA0)] / [1 + j f / (fo(1 + βA0))]

This is again a single-pole response, with

Closed-loop dc gain : Af0 = A0 / (1 + βA0)
Closed-loop BW      : fF  = fo (1 + βA0)
Product             : Af0 × fF = A0 × fo = constant

The factor (1 + βA0) that divides the gain multiplies the bandwidth, so gain × bandwidth = A0·fo = ft, the unity-gain bandwidth, which is fixed for a given op-amp. For the 741, A0 ≈ 2 × 10⁵ and fo ≈ 5 Hz, so GBP ≈ 1 MHz: with a gain of 10 the bandwidth is 100 kHz, with a gain of 100 it is 10 kHz.

Definitions

• Input offset voltage (Vio): the dc voltage that must be applied between the two inputs to make the output zero when both inputs are at ground potential. It comes from mismatch of the input transistors. 741: 1 mV typical, 6 mV max.
• Input offset current (Ios): the difference between the currents flowing into the two inputs when the output is zero, Ios = |IB1 − IB2|. 741: 20 nA typical, 200 nA max.
• Input bias current (IB): the average of the currents flowing into the two input terminals when the output is zero, IB = (IB1 + IB2)/2. It is the base current of the input transistors. 741: 80 nA typical, 500 nA max.

Input resistance of the closed-loop op-amp

The answer depends on the configuration; both are shown.

Inverting amplifier (voltage-shunt feedback):

                Rf
       +------/\/\/-----+
       |                 |
 vin --R1--+--(-)        |
  -> i1    |        >----+---- vo
       GND-+--(+)

The input current i1 flows through R1 into node v− (the op-amp input current is negligible since Ri is very large).

vo = -A·v-          (v+ = 0)
Current through Rf:
  iF = (v- - vo)/Rf = v-(1 + A)/Rf
So, seen from node v-, Rf looks like
  Rf/(1 + A)        (Miller effect)
Node v- to ground: Ri ‖ Rf/(1 + A) ≈ Rf/(1 + A)
Input resistance:
  Rin = vin/i1 = R1 + Rf/(1 + A)
Since A is very large:
  Rin ≈ R1

So the input resistance of the inverting amplifier is set by R1, because the inverting input is a virtual ground. Example: R1 = 10 kΩ, Rf = 100 kΩ, A = 2 × 10⁵: Rin = 10 kΩ + 0.5 Ω ≈ 10 kΩ.

For the non-inverting amplifier (voltage-series feedback), vin drives the + input directly:

vd  = vin - β·vo ,   vo = A·vd ,   β = R1/(R1 + Rf)
vin = vd(1 + Aβ)
iin = vd/Ri
Rif = vin/iin = Ri(1 + Aβ)

Example: Ri = 2 MΩ, A = 2 × 10⁵, β = 0.1 gives Rif = 2 MΩ × 20 001 ≈ 40 GΩ, practically infinite.

Input offset voltage

Input offset voltage (Vio) is the dc differential voltage that must be applied between the inverting and non-inverting inputs of an op-amp to make its output voltage zero. It is caused by mismatch between the input transistors. With feedback it appears at the output as Voo = (1 + Rf/R1)·Vio. For the 741, Vio is 1 mV typical and 6 mV maximum.

Proof that GBP is constant

The open-loop gain of an internally compensated op-amp (e.g. 741) has a single dominant pole at fo:

A(f) = A0 / (1 + j f/fo)
A0 = dc open-loop gain,  fo = open-loop break frequency

Apply negative feedback with feedback factor β (for a non-inverting amplifier β = R1/(R1 + Rf)):

Af(f) = A(f) / (1 + β A(f))
      = [A0/(1 + jf/fo)] / [1 + βA0/(1 + jf/fo)]
      = A0 / (1 + βA0 + jf/fo)
      = [A0/(1 + βA0)] / [1 + j f / (fo(1 + βA0))]

This is again a single-pole response, with

Closed-loop dc gain : Af0 = A0 / (1 + βA0)
Closed-loop BW      : fF  = fo (1 + βA0)
Product             : Af0 × fF = A0 × fo = constant

The factor (1 + βA0) that divides the gain multiplies the bandwidth, so gain × bandwidth = A0·fo = ft, the unity-gain bandwidth, which is fixed for a given op-amp. For the 741, A0 ≈ 2 × 10⁵ and fo ≈ 5 Hz, so GBP ≈ 1 MHz: with a gain of 10 the bandwidth is 100 kHz, with a gain of 100 it is 10 kHz.

This shows that for an op-amp, gain can be traded for bandwidth, but their product cannot be increased.

The input impedance of the inverting amplifier is the resistance seen by the signal source, Rin = vin/iin. Take a practical op-amp with open-loop gain A and very large input resistance Ri.

                Rf
       +------/\/\/-----+
       |                 |
 vin --R1--+--(-)        |
  -> i1    |        >----+---- vo
       GND-+--(+)

The input current i1 flows through R1 into node v− (the op-amp input current is negligible since Ri is very large).

vo = -A·v-          (v+ = 0)
Current through Rf:
  iF = (v- - vo)/Rf = v-(1 + A)/Rf
So, seen from node v-, Rf looks like
  Rf/(1 + A)        (Miller effect)
Node v- to ground: Ri ‖ Rf/(1 + A) ≈ Rf/(1 + A)
Input resistance:
  Rin = vin/i1 = R1 + Rf/(1 + A)
Since A is very large:
  Rin ≈ R1

So the input resistance of the inverting amplifier is set by R1, because the inverting input is a virtual ground. Example: R1 = 10 kΩ, Rf = 100 kΩ, A = 2 × 10⁵: Rin = 10 kΩ + 0.5 Ω ≈ 10 kΩ.

Answer: Rin = R1 + Rf/(1 + A) ≈ R1.

This is low compared with the non-inverting amplifier (Rif = Ri(1 + Aβ)), so the source must be able to drive R1; R1 is chosen large enough (e.g. 10 kΩ or more) not to load the source.

Input bias currents IB1 and IB2 are the dc base currents drawn by the input transistors of the op-amp. They flow through the external resistors and create a dc output voltage even when the input signal is zero.

                 Rf
          +----/\/\/----+
          |             |
 Vi --R1--+--> IB1 -(-) |
                     >--+---- Vo
     +-----> IB2 ---(+)
     |
   Rcomp
     |
    GND

Take Vi = 0 (only bias currents act). IB1 flows into the inverting input and IB2 into the non-inverting input.

Without compensation (Rcomp = 0): the non-inverting input is at 0 V, so the inverting input is also at 0 V (virtual ground). No current flows in R1, so all of IB1 comes through Rf:

Vo = IB1 · Rf

e.g. IB = 500 nA, Rf = 1 MΩ gives 0.5 V of output error with no input.

With compensation resistor Rcomp at the non-inverting input:

V+ = -IB2·Rcomp = V-
KCL at inverting node:
  (0 - V-)/R1 + (Vo - V-)/Rf = IB1
  Vo = IB1·Rf + V-(1 + Rf/R1)
     = IB1·Rf - IB2·Rcomp(1 + Rf/R1)
Choose Rcomp(1 + Rf/R1) = Rf, i.e.
  Rcomp = R1·Rf/(R1 + Rf) = R1 ‖ Rf
Then
  Vo = Rf (IB1 - IB2) = Rf · Ios

Since Ios is typically 5 to 10 times smaller than IB, the error falls a lot. The rule is: both inputs should see the same dc resistance to ground.

Other ways to reduce the effect of bias currents:

• Use op-amps with low IB (FET-input or super-β types, e.g. LF351, CA3140 with IB in pA).
• Keep Rf (and all resistors) low, since the error is IB·Rf or Ios·Rf.
• Use a T-network feedback to get high gain with smaller resistors.
• Use the offset-null terminals (pins 1 and 5 on the 741 with a 10 kΩ pot) or an external balancing network to trim the remaining output offset to zero.
• For ac amplifiers, use capacitor coupling so the dc gain is 1.

Input bias current and input offset current

• Input bias current (IB): the average of the dc currents flowing into the two inputs when the output is zero, IB = (IB1 + IB2)/2. It is the base current needed to bias the input transistors (741: 80 nA typical, 500 nA max).
• Input offset current (Ios): the difference between the two input currents, Ios = |IB1 − IB2|, caused by β mismatch (741: 20 nA typical, 200 nA max).

Effect of input bias currents on output voltage

                 Rf
          +----/\/\/----+
          |             |
 Vi --R1--+--> IB1 -(-) |
                     >--+---- Vo
     +-----> IB2 ---(+)
     |
   Rcomp
     |
    GND

With Vi = 0 and Rcomp = 0, the inverting input is at virtual ground, so no current flows in R1 and the whole of IB1 must come from the output through Rf:

Vo = IB1 · Rf

So the output has a dc error with no input. Example: IB1 = 500 nA, Rf = 1 MΩ gives Vo = 0.5 V. This error adds to the signal, shifts the operating point, and in integrators (Rf replaced by a capacitor) charges the capacitor until the output saturates.

Reducing the effect of input bias currents

Compensating resistor: connect Rcomp from the non-inverting input to ground:

V+ = V- = -IB2·Rcomp
Vo = IB1·Rf - IB2·Rcomp(1 + Rf/R1)
With Rcomp = R1 ‖ Rf = R1·Rf/(R1 + Rf):
Vo = Rf (IB1 - IB2) = Rf · Ios

Since Ios is much smaller than IB, the output error drops (in the example above, with Ios = 200 nA it falls from 0.5 V to 0.2 V).

Other ways to reduce the effect of bias currents:

• Use op-amps with low IB (FET-input or super-β types, e.g. LF351, CA3140 with IB in pA).
• Keep Rf (and all resistors) low, since the error is IB·Rf or Ios·Rf.
• Use a T-network feedback to get high gain with smaller resistors.
• Use the offset-null terminals (pins 1 and 5 on the 741 with a 10 kΩ pot) or an external balancing network to trim the remaining output offset to zero.
• For ac amplifiers, use capacitor coupling so the dc gain is 1.

Given: inverting amplifier with R1 = 10 kΩ, Rf = 330 kΩ, so |Av| = 330/10 = 33. SR = 0.5 V/µs = 0.5 × 10⁶ V/s.

For an input Vp sin ωt, the output is 33·Vp sin ωt and its maximum slope is ω × 33 × Vp. The output is undistorted only if this is ≤ SR.

Check each signal

V1: 10⁶     × 33 × 0.01 = 0.33  × 10⁶ V/s < 0.5 → OK
V2: 3.5×10⁵ × 33 × 0.05 = 0.5775× 10⁶ V/s > 0.5 → distorted
V3: 2×10⁵   × 33 × 0.1  = 0.66  × 10⁶ V/s > 0.5 → distorted
V4: 5×10⁴   × 33 × 0.1  = 0.165 × 10⁶ V/s < 0.5 → OK

V2 and V3 will be distorted by slew-rate limiting; V1 and V4 will not.

New feedback resistor

For each signal the maximum gain allowed is Av(max) = SR/(ω·Vp):

V1: 0.5×10⁶ / (10⁶ × 0.01)     = 50
V2: 0.5×10⁶ / (3.5×10⁵ × 0.05) = 28.57
V3: 0.5×10⁶ / (2×10⁵ × 0.1)    = 25
V4: 0.5×10⁶ / (5×10⁴ × 0.1)    = 100

The smallest limit is 25 (set by V3), so the gain must be ≤ 25:

Rf ≤ 25 × R1 = 25 × 10 kΩ = 250 kΩ

Answer: V2 and V3 are distorted; use Rf ≤ 250 kΩ (e.g. a standard 240 kΩ or 220 kΩ) so that none of the signals is distorted. (This treats each signal applied separately, which is the usual reading; if all four were applied together, the slopes could add and a still smaller gain would be needed.)

Noise is any unwanted random signal that appears at the output of an op-amp circuit and is not part of the input signal. It sets the smallest signal the amplifier can handle and limits the signal-to-noise ratio. It can be external (pickup from power lines, motors, radio sources, ground loops) or internal (generated inside resistors and transistors).

Types of noise in op-amp circuits:

• Thermal (Johnson) noise: random motion of electrons in every resistor. RMS voltage vn = √(4kTRB), where k = 1.38 × 10⁻²³ J/K, T in kelvin, R in ohms and B the bandwidth. A 1 kΩ resistor at 300 K gives about 4 nV/√Hz. It is white (flat with frequency).
• Shot noise: due to random crossing of charge carriers across a junction; noise current in = √(2qIB·B), q = 1.6 × 10⁻¹⁹ C. It is present in the bias currents of the input transistors.
• Flicker (1/f) noise: power increases as frequency falls; dominant below the corner frequency (about 10 Hz to 1 kHz), caused by surface defects.
• Popcorn (burst) noise: sudden step changes in bias current due to contamination; heard as popping in audio.

Noise model: an op-amp's internal noise is represented by a noise voltage source en (nV/√Hz) in series with the input and noise current sources in (pA/√Hz) at each input, driving a noiseless op-amp.

              Rf (noise 4kTRf)
        +-----/\/\/-----+
        |  in           |
 R1 ----+-----(-)       |
 (4kTR1)          >-----+---- eno
 Rs --[en]--+--(+)
 (4kTRs)    in

All the input-referred noise sources are amplified by the noise gain (1 + Rf/R1), not by the signal gain. The independent sources add as root-sum-of-squares:

eni² = en² + (in·Rs)² + (in·R1‖Rf)²
       + 4kT(Rs + R1‖Rf)          per Hz
Eno  = (1 + Rf/R1) · eni · √B     (rms)

Measures to minimize noise:

1. Use low-value resistors (thermal noise and in·R terms grow with R); use metal-film resistors, not carbon.
2. Limit the bandwidth to what the signal needs (noise ∝ √B): add a small capacitor across Rf or a filter.
3. Choose a low-noise op-amp: low en (bipolar input, e.g. OP27) for low source resistance; low in (FET input) for high source resistance.
4. Keep the noise gain low; take gain in the first stage so later-stage noise is less significant.
5. Balance the resistances at the two inputs but bypass Rcomp with a capacitor so its noise is not amplified.
6. Decouple power supply pins with 0.1 µF capacitors near the IC; use proper grounding (star ground) and shielded cables against pickup.
7. Keep the circuit cool and away from noisy (switching) sources; use ac coupling or chopper op-amps to avoid 1/f noise at low frequencies.

Given: R1 = 100 kΩ, Rf = 10 MΩ, 741 with Vios = 6 mV, IB = 500 nA, Ios = 200 nA (maximum values).

Noise gain: 1 + Rf/R1 = 1 + 10 MΩ/100 kΩ = 101

(i) Output offset due to input bias current

With the + input grounded, the − input is at virtual ground, so IB flows through Rf:

Vo(IB) = Rf · IB = 10 × 10⁶ × 500 × 10⁻⁹ = 5 V

(ii) Output offset due to input offset voltage

Vios is amplified by the noise gain:

Vo(Vios) = (1 + Rf/R1) · Vios = 101 × 6 mV = 0.606 V

(iii) Compensating resistor

To cancel the effect of IB, both inputs must see the same dc resistance:

Rcomp = R1 ‖ Rf = (100 kΩ × 10 MΩ)/(100 kΩ + 10 MΩ)
      = 10¹² / 10.1 × 10⁶ = 99.01 kΩ

(A standard 100 kΩ resistor would be used.)

(iv) Maximum output offset with Rcomp connected

With Rcomp = R1‖Rf, the bias-current error becomes Ios·Rf:

Vo(Ios) = Rf · Ios = 10 × 10⁶ × 200 × 10⁻⁹ = 2 V

The offset voltage error is still present, so in the worst case both add:

Vo(total, max) = Vo(Ios) + Vo(Vios) = 2 + 0.606 = 2.606 V

Answers: (i) 5 V, (ii) 0.606 V, (iii) Rcomp = 99.01 kΩ, (iv) 2 V due to Ios, or 2.606 V total including Vios. Without Rcomp the worst-case total would be 5 + 0.606 = 5.606 V. The remaining offset can be removed with the 741 offset-null pot.

Gain-bandwidth product of a practical op-amp

A practical (internally compensated) op-amp has a single dominant pole, so its open-loop gain is A(f) = A0/(1 + jf/fo). For the 741, A0 ≈ 2 × 10⁵ and fo ≈ 5 Hz. When negative feedback with factor β is applied:

Closed-loop gain: Af = A0/(1 + A0β)
Bandwidth:        fF = fo(1 + A0β)
Af × fF = A0 × fo = ft (constant)
741: GBP = 2 × 10⁵ × 5 Hz = 1 MHz

So the product of closed-loop gain and bandwidth is constant and equal to the unity-gain frequency ft. Reducing gain by a factor increases bandwidth by the same factor (gain 10 → BW 100 kHz; gain 100 → BW 10 kHz). This lets a designer find the bandwidth for a given gain: BW = GBP/gain (using the noise gain 1 + Rf/R1).

Output resistance of an amplifier using a practical op-amp

Model the op-amp by its open-loop gain A, input resistance Ri (very large, ignored) and output resistance Ro. To find the closed-loop output resistance, set the input source to zero, apply a test voltage vx at the output and find the current ix drawn.

             Rf
   +-------/\/\/--------+
   |                    |
   R1  v- ---(-)        |
   |              Ro    |
  GND GND ---(+)--/\/\--+--- vx (test), ix in
            [A·vd]

Feedback voltage at inverting input:
  v- = vx·R1/(R1 + Rf) = β·vx
  vd = v+ - v- = -β·vx
Current through Ro:
  io = (vx - A·vd)/Ro = vx(1 + Aβ)/Ro
Current through R1 + Rf:
  iF = vx/(R1 + Rf)   (very small, neglected)
  ix ≈ io = vx(1 + Aβ)/Ro
Rof = vx/ix = Ro / (1 + Aβ),   β = R1/(R1 + Rf)

Because the output voltage is sampled and fed back (voltage feedback), the output resistance is divided by (1 + Aβ). Example: 741 with Ro = 75 Ω, A = 2 × 10⁵ and β = 0.1 gives Rof = 75/(1 + 2 × 10⁴) ≈ 3.75 mΩ, practically zero. The same result holds for the inverting and non-inverting amplifiers, since with the input grounded both have the same feedback network.

Input offset voltage and input offset current

• Input offset voltage (Vio): the dc voltage that must be applied between the two inputs to make the output zero when both inputs are at ground potential. It comes from mismatch of the input transistors. 741: 1 mV typical, 6 mV max.
• Input offset current (Ios): the difference between the currents flowing into the two inputs when the output is zero, Ios = |IB1 − IB2|. 741: 20 nA typical, 200 nA max.

Output resistance of the closed-loop op-amp

Model the op-amp by its open-loop gain A, input resistance Ri (very large, ignored) and output resistance Ro. To find the closed-loop output resistance, set the input source to zero, apply a test voltage vx at the output and find the current ix drawn.

             Rf
   +-------/\/\/--------+
   |                    |
   R1  v- ---(-)        |
   |              Ro    |
  GND GND ---(+)--/\/\--+--- vx (test), ix in
            [A·vd]

Feedback voltage at inverting input:
  v- = vx·R1/(R1 + Rf) = β·vx
  vd = v+ - v- = -β·vx
Current through Ro:
  io = (vx - A·vd)/Ro = vx(1 + Aβ)/Ro
Current through R1 + Rf:
  iF = vx/(R1 + Rf)   (very small, neglected)
  ix ≈ io = vx(1 + Aβ)/Ro
Rof = vx/ix = Ro / (1 + Aβ),   β = R1/(R1 + Rf)

Because the output voltage is sampled and fed back (voltage feedback), the output resistance is divided by (1 + Aβ). Example: 741 with Ro = 75 Ω, A = 2 × 10⁵ and β = 0.1 gives Rof = 75/(1 + 2 × 10⁴) ≈ 3.75 mΩ, practically zero. The same result holds for the inverting and non-inverting amplifiers, since with the input grounded both have the same feedback network.

Slew rate

Slew rate (SR) is the maximum rate of change of output voltage per unit time that an op-amp can produce, SR = (dVo/dt)max, usually in V/µs (0.5 V/µs for the 741). It is caused by the limited current available to charge the internal compensation capacitor (SR = Imax/C).

Checking for distortion

Given: Rf = 330 kΩ, R1 = 10 kΩ, SR = 0.5 V/µs, vin = 0.1 sin(200000t) V.

|Av| = Rf/R1 = 330/10 = 33
Vm   = 33 × 0.1 = 3.3 V   (output peak)
ω    = 2 × 10⁵ rad/s,  f = ω/2π = 31.83 kHz
Required slope = ω·Vm = 2 × 10⁵ × 3.3
               = 0.66 × 10⁶ V/s = 0.66 V/µs

Since 0.66 V/µs > 0.5 V/µs, the output will be distorted due to slew-rate limiting. (Full-power bandwidth for 3.3 V peak: fmax = SR/(2πVm) = 0.5 × 10⁶/(2π × 3.3) = 24.11 kHz < 31.83 kHz.)

Remedies

1. Reduce the gain: maximum undistorted output peak Vm = SR/ω = 0.5 × 10⁶/(2 × 10⁵) = 2.5 V, so gain ≤ 2.5/0.1 = 25, i.e. Rf ≤ 25 × 10 kΩ = 250 kΩ.
2. Use an op-amp with higher slew rate: SR ≥ 0.66 V/µs (e.g. LF351, 13 V/µs).
3. Reduce the input amplitude: Vin(peak) ≤ 2.5/33 = 75.8 mV.

Answer: distorted (0.66 V/µs required > 0.5 V/µs); remedy Rf ≤ 250 kΩ or a faster op-amp.

A voltage follower has gain 1, so ideally the output equals the input square wave: 2 V peak-to-peak, i.e. a step of 2 V at every edge (from −1 V to +1 V and back). The output cannot change faster than SR = 0.5 V/µs, so each edge becomes a ramp.

Time to slew through 2 V:
  t_r = ΔV / SR = 2 V / 0.5 V/µs = 4 µs

(i) f = 100 Hz

T = 1/100 = 10 ms,  half-period = 5 ms
Ramp time / half period = 4 µs / 5 ms = 0.08 %

The 4 µs ramps are negligible, so the output is practically a perfect square wave of ±1 V.

 +1 V  ____________            ____________
      |            |          |
      |            |          |
 -1 V |            |__________|
      0           5 ms       10 ms      t
  (each edge is a 4 µs ramp, too short to see)

(ii) f = 100 kHz

T = 1/100 kHz = 10 µs,  half-period = 5 µs
Ramp takes 4 µs, flat top lasts 5 - 4 = 1 µs

The output is a trapezoidal wave: it rises linearly from −1 V to +1 V in 4 µs, stays at +1 V for 1 µs, falls linearly to −1 V in 4 µs, stays for 1 µs, and repeats. The peak-to-peak value is still 2 V because the 4 µs ramp fits inside the 5 µs half-period.

 +1 V      ___         ___
          /   \       /   \
         /     \     /     \
 -1 V __/       \___/       \__
       0   4  5   9 10  14 15   t (µs)
  rise 0-4 µs, flat 4-5 µs, fall 5-9 µs,
  flat 9-10 µs, next rise 10-14 µs ...

If the frequency were raised above 125 kHz (half-period < 4 µs), the output would become a triangle wave of reduced amplitude.

Effect of input bias current

The input transistors of an op-amp draw small dc base currents IB1 (inverting input) and IB2 (non-inverting input). These flow through external resistors and produce an output voltage even with zero input.

                 Rf
          +----/\/\/----+
          |             |
 Vi --R1--+--> IB1 -(-) |
                     >--+---- Vo
     +-----> IB2 ---(+)
     |
   Rcomp
     |
    GND

With Vi = 0 and Rcomp = 0, the inverting input is at virtual ground, so all of IB1 flows through Rf:

Vo = IB1·Rf     (e.g. 500 nA × 1 MΩ = 0.5 V)

Adding Rcomp = R1‖Rf at the non-inverting input makes V− = −IB2·Rcomp, and

Vo = IB1·Rf - IB2·Rcomp(1 + Rf/R1) = Rf(IB1 - IB2) = Rf·Ios

so only the much smaller offset current causes error.

Closed-loop output impedance of the inverting amplifier

Model the op-amp by its open-loop gain A, input resistance Ri (very large, ignored) and output resistance Ro. To find the closed-loop output resistance, set the input source to zero, apply a test voltage vx at the output and find the current ix drawn.

             Rf
   +-------/\/\/--------+
   |                    |
   R1  v- ---(-)        |
   |              Ro    |
  GND GND ---(+)--/\/\--+--- vx (test), ix in
            [A·vd]

Feedback voltage at inverting input:
  v- = vx·R1/(R1 + Rf) = β·vx
  vd = v+ - v- = -β·vx
Current through Ro:
  io = (vx - A·vd)/Ro = vx(1 + Aβ)/Ro
Current through R1 + Rf:
  iF = vx/(R1 + Rf)   (very small, neglected)
  ix ≈ io = vx(1 + Aβ)/Ro
Rof = vx/ix = Ro / (1 + Aβ),   β = R1/(R1 + Rf)

Because the output voltage is sampled and fed back (voltage feedback), the output resistance is divided by (1 + Aβ). Example: 741 with Ro = 75 Ω, A = 2 × 10⁵ and β = 0.1 gives Rof = 75/(1 + 2 × 10⁴) ≈ 3.75 mΩ, practically zero. The same result holds for the inverting and non-inverting amplifiers, since with the input grounded both have the same feedback network.

Slew rate

Slew rate (SR) is the maximum rate of change of output voltage per unit time that an op-amp can produce, SR = (dVo/dt)max, usually in V/µs (0.5 V/µs for the 741). For a sine output Vm sin 2πft, the maximum slope is 2πf·Vm, so the output is undistorted only if 2πf·Vm ≤ SR.

Maximum peak input

Given: bandwidth (highest signal frequency) f = 20 kHz, closed-loop gain = 20, SR = 1 V/µs = 10⁶ V/s.

Maximum undistorted output peak:
  Vm = SR / (2πf)
     = 10⁶ / (2π × 20 × 10³)
     = 7.958 V
Maximum peak input:
  Vin(peak) = Vm / gain = 7.958 / 20
            = 0.398 V

Answer: maximum peak input ≈ 0.398 V (398 mV), giving a 7.96 V peak output at 20 kHz. A larger input would make the output slew-rate limited (triangular) at the top of the band.

Input bias currents are the dc base (or gate) currents of the input transistors. The current into the non-inverting input is called the positive input bias current IB⁺ (or IB2), and the current into the inverting input the negative input bias current IB⁻ (or IB1). (The currents flow into the op-amp for NPN input transistors and out of it for PNP inputs; only the sign of the error changes.)

                 Rf
          +----/\/\/----+
          |             |
 Vi --R1--+--> IB1 -(-) |
                     >--+---- Vo
     +-----> IB2 ---(+)
     |
   Rcomp
     |
    GND

Effect of IB⁻ (inverting input)

With Vi = 0 and Rcomp = 0, the inverting input is a virtual ground, so no current flows in R1 and IB⁻ must flow from the output through Rf:

Vo1 = +IB⁻ · Rf

Effect of IB⁺ (non-inverting input)

IB⁺ flows through Rcomp and makes V+ = −IB⁺·Rcomp. The circuit amplifies this as a non-inverting amplifier:

Vo2 = -IB⁺ · Rcomp · (1 + Rf/R1)

Total effect

By superposition:

Vo = IB⁻·Rf - IB⁺·Rcomp(1 + Rf/R1)

The two currents produce outputs of opposite polarity, so they can be made to cancel.

Methods of reduction

1. Compensating resistor: choose Rcomp(1 + Rf/R1) = Rf, i.e. Rcomp = R1‖Rf. Then

Vo = Rf(IB⁻ - IB⁺) = Rf·Ios

which is much smaller since Ios << IB. 2. Use FET-input or super-β op-amps with very small bias currents (pA). 3. Use smaller resistor values (or a T-feedback network for high gain), since the error is proportional to Rf. 4. Null the remaining error with the offset-null pot (741: 10 kΩ between pins 1 and 5). 5. In ac amplifiers, use coupling capacitors so the dc gain is unity.

• CMRR (common-mode rejection ratio): the ratio of differential gain to common-mode gain, CMRR = |Ad/Acm|, usually in dB: CMRR = 20 log10|Ad/Acm|. It shows how well the op-amp rejects signals (noise, hum) common to both inputs. For the 741 it is about 90 dB; ideal is infinite.
• PSRR (power supply rejection ratio, also SVRR): the change in input offset voltage per unit change in one supply voltage, the other supply being constant: PSRR = ΔVio/ΔV, in µV/V (or dB). It shows how well the op-amp rejects supply ripple and variation. For the 741 it is 30 µV/V typical; smaller is better.
• Slew rate (SR): the maximum rate of change of output voltage, SR = (dVo/dt)max, in V/µs. It is set by the current charging the internal compensation capacitor (SR = Imax/C). For the 741 it is 0.5 V/µs. A sine output of peak Vm is undistorted only up to fmax = SR/(2πVm).

Noise is any unwanted random signal at the output of an op-amp circuit. It limits the smallest signal that can be amplified (signal-to-noise ratio).

Sources:

• Thermal (Johnson) noise in resistors: vn = √(4kTRB); white noise.
• Shot noise in junction currents: in = √(2qI·B).
• Flicker (1/f) noise: large at low frequencies, below the corner frequency.
• Popcorn (burst) noise: random step changes due to contamination.
• External noise: pickup from mains (50 Hz), switching circuits, ground loops.

Model: the op-amp is treated as noiseless with an input noise voltage source en (nV/√Hz) and noise current sources in (pA/√Hz). Resistors add 4kTR. All input noise is amplified by the noise gain (1 + Rf/R1), and independent sources add as root-sum-of-squares:

Eno = (1 + Rf/R1)·√[en² + (in·R)² + 4kTR]·√B

Reduction: use low-value metal-film resistors, limit bandwidth (capacitor across Rf), choose a low-noise op-amp suited to the source resistance (bipolar for low R, FET for high R), keep noise gain low, decouple supplies and use shielding and proper grounding.