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Dual slope ADC: RC independence, noise immunity

Short answer

In dual-slope ADC, the counter output N2 = N1 * Vin / Vref because the charge balance Vin·T1/RC = Vref·T2/RC cancels RC. It is noise-immune because it averages the input over T1, and if T1 is a multiple of the mains period, power-line interference integrates to zero.

Explain the working principle of a dual slope ADC and prove that its output is independent of RC time constant. Justify that the converter is inherently noise immune.

A dual slope ADC converts a voltage into a time interval by integrating twice: first the input for a fixed time, then a reference until the integrator returns to zero. The second time, measured by a counter, is the digital output.

Block diagram

 Vin  --o S1                  C
 -Vref--o--+--[R]--+---------||-------+
                   |                  |
                  (-)\                |
                      >---------------+-- Vo1
                  (+)/                    |
                   |                 [COMPARATOR]
                  GND                (zero detect)
                                          |
  CLOCK --> [ n-bit COUNTER ] <--> [ CONTROL LOGIC ]
                 |                       |
            digital output         controls S1, reset

Working principle

  1. Reset: the counter is cleared and C is discharged.
  2. Phase 1 (fixed time T1): S1 connects Vin. The integrator ramps while the counter counts N1 = 2ⁿ fixed pulses, so T1 = N1·Tclk.
Vo1(T1) = −(1/RC) ∫₀^T1 Vin dt = −Vin·T1/RC
  1. Phase 2 (variable time T2): at counter overflow S1 switches to −Vref. The output ramps back with a fixed slope Vref/RC. The counter restarts from zero.
  2. When Vo1 crosses zero, the comparator stops the counter. The count N2 is the result.
 |Vo1|
   |     /\
   |    /  \           up-slope ∝ Vin
   |   /    \          down-slope ∝ Vref (fixed)
   |  /      \
   |_/________\______ t
     |<-T1 ->|<-T2->|

Proof that output is independent of RC

The charge gained in phase 1 equals the charge removed in phase 2:

Vin·T1 / RC = Vref·T2 / RC

RC is on both sides and cancels:

T2 = T1 · Vin/Vref
N2·Tclk = N1·Tclk · Vin/Vref
N2 = N1 · Vin / Vref

The result has no R, no C and not even the clock period. It depends only on Vin/Vref and the fixed count N1. Slow drift in R, C or clock frequency therefore does not cause error, as long as it stays the same during one conversion.

Why it is inherently noise immune

  • The converter measures the average of Vin over T1, not an instant value: N2 ∝ (1/T1)∫Vin dt.
  • Random noise has zero average, so integration removes most of it.
  • If T1 is an exact multiple of the mains period (for example 20 ms for 50 Hz), any 50 Hz hum and its harmonics integrate to exactly zero:
∫₀^T1 Vm sin(2π·50t) dt = 0   when T1 = k × 20 ms

So power-line interference is rejected completely. This is why dual slope ADCs are used in digital multimeters and panel meters.

✓ Answer checked by Claude Opus 5.5 (high effort)

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