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Dual slope and flash A/D conversion

Short answer

The dual-slope ADC integrates the input for a fixed time T1, then a reference of opposite polarity until the integrator returns to zero, giving a count N2 = N1·Vin/Vref that is independent of RC and clock. The flash ADC uses a resistor ladder and 2^n−1 comparators to compare the input simultaneously, converting via priority encoder in one comparator delay for highest speed.

Explain how A/D conversion can be achieved by using dual slope method and flash method.

Dual-slope ADC

This is an indirect, integrating ADC. It integrates the unknown input for a fixed time, then integrates a reference of opposite polarity until the integrator output returns to zero. The second time is proportional to the input.

 Vin --+
       v        +----------+
     [SW]--[R]--| Integr.  |--+--> [Comparator] --> control
 -Vref-+     C  | (op-amp) |                         logic
                +----------+                          |
                                         clock -> [Counter] -> output

Working:

  1. Phase 1 (fixed time T1): the counter is cleared and the switch connects Vin to the integrator. The integrator output ramps down for T1 = N1 clock periods (the counter counts up to its full value N1). At the end of T1 the integrator output is V = −Vin·T1/(RC).
  2. Phase 2 (variable time T2): the switch connects −Vref; the output ramps back up with a fixed slope Vref/(RC), and the counter counts again until the comparator detects the zero crossing. Vref·T2/(RC) = Vin·T1/(RC)

T2 = T1·Vin/Vref, so the count N2 = N1·Vin/Vref gives the digital value.

The result does not depend on R, C or the clock frequency. The converter rejects noise by averaging; if T1 is a multiple of the power-line period, 50 Hz noise cancels. It has high accuracy but is slow, and is used in digital voltmeters.

Flash (parallel) ADC

This is the fastest ADC. An n-bit flash ADC needs 2ⁿ − 1 comparators.

 Vref
   |
  [R]
   +----(-)[C7]---+
  [R]             |
   +----(-)[C6]---+
  [R]     ...     +--> [Priority  ] --> 3-bit
   +----(-)[C2]---+    [ encoder  ]     binary output
  [R]             |
   +----(-)[C1]---+
  [R]
   |
  gnd

 Vin is applied to the (+) input of every comparator.
 3-bit: 8 equal resistors, 7 comparators (taps at 1/8, 2/8, ..., 7/8 of Vref).

Working: a chain of equal resistors divides Vref into 2ⁿ equal steps and gives the reference levels to the comparators. Vin is applied to all comparators at once. Every comparator whose reference is below Vin outputs 1, and the others output 0 (thermometer code). A priority encoder converts this code to binary. (Some designs use R/2 at the bottom of the chain to shift the thresholds by half an LSB, reducing the quantisation error to ±½ LSB.)

Example (3-bit, Vref = 8 V, thresholds 1 V to 7 V): Vin = 5.3 V; the comparators with references 1 to 5 V are high, so 5 comparators are on and the output is 101.

Conversion takes only one comparator-plus-encoder delay (nanoseconds), but the number of comparators doubles with each extra bit, so the converter is costly and power hungry, and is limited to about 8 to 10 bits.

✓ Answer checked by Claude Opus 5.5 (high effort)

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