- 2070 Asar · 2+5 marks
Sigma-delta applications; 8-bit dual slope numerical
Short answer
Sigma-delta ADC is used in digital audio, precision measurement, and data acquisition. For the dual-slope ADC, the integrator reaches Vmax = 2 V after 160 µs. With Vref = 1 V, the digital output is 125 (01111101 in 8-bit).
State the application of sigma delta ADC. In an 8-bit Dual Slope ADC, R = 20 KΩ and C = 0.001 μF. An analog input signal of -0.25V is integrated for t1 = 160 μs. What is the maximum voltage reached in the integration? If the counter is clocked at 3.125 MHz what is the digital output after the conversion?
Applications of sigma-delta ADC
A sigma-delta (ΣΔ) ADC uses oversampling, noise shaping and digital filtering. It gives very high resolution (16 to 24 bits) at low to medium speed. It is used in:
- Digital audio: CD and studio recording, codecs, mobile phones
- Precision measurement: weighing scales, strain gauges, thermocouples
- Digital voltmeters and data acquisition
- Voice-band telecommunication, modems and seismic sensors
Dual slope ADC numerical
Given: n = 8, R = 20 kΩ, C = 0.001 µF, Vin = −0.25 V, t1 = 160 µs, clock = 3.125 MHz.
1. Integrator time constant
RC = 20×10³ × 0.001×10⁻⁶ = 20×10⁻⁶ s = 20 µs
2. Maximum voltage reached during integration The inverting integrator output after t1 is:
Vo(max) = −(1/RC) ∫₀^t1 Vin dt = −Vin·t1/RC
= −(−0.25)(160 µs)/(20 µs)
= +2 V
So the integrator output reaches 2 V.
3. Digital output The reference voltage is not given, so assume Vref = 1 V (opposite in polarity to Vin). During de-integration the output falls from 2 V to 0 at slope Vref/RC:
t2 = Vo(max) · RC / Vref = 2 × 20 µs / 1 = 40 µs
Clock period Tclk = 1/3.125 MHz = 0.32 µs
N = t2 / Tclk = 40 / 0.32 = 125
In binary (8 bits): 125 = 01111101.
Check with the dual slope relation: t2 = t1·|Vin|/Vref = 160 × 0.25/1 = 40 µs, which matches.
Answer: Vmax = 2 V. Digital output = 125 = 01111101₂ (taking Vref = 1 V). For any other Vref (in volts), N = 125/Vref.
✓ Answer checked by Claude Opus 5.5 (high effort)
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