Sync counter for sequence 000,001,011,111,110,100

Asynchronous counter

An asynchronous (ripple) counter is a counter in which the external clock is applied only to the first flip-flop, and every other flip-flop is clocked by the output of the preceding flip-flop. The flip-flops therefore change state one after another, not together. It is simple but slow, and it shows short false states while the change ripples through.

Design of the synchronous counter: 000, 001, 011, 111, 110, 100, 000 …

Step 1: 6 states, so 3 JK flip-flops ($Q_2Q_1Q_0$) with a common clock. Unused states: 010 and 101 (don't cares).

Step 2: Excitation table (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)

Step 3: K-maps

Step 4: Equations

The minimum groups give $J_2 = Q_1$, but then the unused states form a closed loop 010 → 101 → 010, so a counter that powers up in 010 or 101 would never enter the sequence (lock-out). Taking the 1-cell 011 alone, $J_2 = Q_1Q_0$, removes this problem at the cost of one AND gate:

$$\begin{aligned} &J_2 = Q_1Q_0,\quad K_2 = \overline{Q_1} \\ &J_1 = Q_0,\quad K_1 = \overline{Q_0} \\ &J_0 = \overline{Q_2},\quad K_0 = Q_2 \end{aligned}$$

Check of unused states (with $J_2 = Q_1Q_0$)

So the counter is self-starting.

Step 5: Circuit diagram

   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = Q2'   K0 = Q2
J1 = Q0    K1 = Q0'
J2 = Q1.Q0 K2 = Q1'

The sequence is that of a 3-bit Johnson (twisted-ring) counter: in the count, $Q_1$ copies $Q_0$, $Q_2$ copies $Q_1$, and $Q_0$ takes the inverted $Q_2$.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ____________|‾‾‾‾‾‾‾‾‾‾‾|_______
Q1   ________|‾‾‾‾‾‾‾‾‾‾‾|___________
Q0   ____|‾‾‾‾‾‾‾‾‾‾‾|___________|‾‾‾
Cnt  000  001 011 111 110 100 000 001