Dual slope ADC working; why accurate

A dual slope ADC is an integrating ADC. It integrates the unknown input for a fixed time and then integrates a known reference of opposite polarity until the integrator returns to zero. The time taken in the second phase, measured by a counter, is proportional to the input.

        S1
 Vin --o\      R        C
         o---/\/\/--+--||--+
 -Vref -o/          |       |
                    +-(-)   |
               GND --(+)>---+-- Vo1 --+
                   integrator         |
                                 comparator
                                (Vo1 vs 0 V)
                                      |
 clock --> [ control logic ] <--------+
                 |      |
            switch S1  [ n-bit counter ] -> digital
                                            output

Working

1. Reset: the counter is cleared and the capacitor is discharged, so Vo1 = 0.
2. Phase 1 (fixed time T1): S1 connects Vin (positive) to the integrator. The output ramps down with slope −Vin/RC. The counter counts until it overflows after N1 = 2ⁿ clock pulses, so T1 = 2ⁿ·Tc (fixed).

Vo1(T1) = -Vin·T1/(RC)

3. Phase 2 (variable time T2): at overflow the control logic switches S1 to −Vref and the counter restarts from zero. The output now ramps up with fixed slope Vref/RC. When Vo1 reaches 0 V the comparator changes state and the counter stops at N2.

Vin·T1/(RC) = Vref·T2/(RC)
T2 = T1·Vin/Vref
N2·Tc = N1·Tc·Vin/Vref
N2 = 2ⁿ · Vin / Vref

The count N2 is the digital output and is directly proportional to Vin.

Vo1
 0 +-.                 .---
   |  \               /
   |   \             /
   |    \           /
   |     \         /
   |      \       /
   |       \     /
   |        \   /
   |         \ /
   |          V
   |<-- T1 -->|<- T2 ->|
   slope -Vin/RC   slope +Vref/RC (fixed)

Why the output is accurate

• R, C and clock frequency cancel: they appear on both sides of Vin·T1/RC = Vref·T2/RC, and the same clock times both phases, so their tolerance, drift and ageing do not affect the result. Accuracy depends only on Vref.
• Noise rejection: the input is averaged over T1, so random noise is reduced. If T1 is a multiple of the mains period (20 ms for 50 Hz), mains hum integrates to zero.
• Comparator offset has little effect because the comparator only detects the zero crossing at the same level each time.
• Good linearity, no missing codes, and high resolution are possible.

The disadvantage is low speed (tens of conversions per second), so it is used in digital multimeters and panel meters.