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Interface two 8K x 8 ROM at 4000H

Short answer

Each 8KB ROM uses A12–A0; A15–A13 select chips. Decoder: 74LS138 with C,B,A = A15,A14,A13, G1=+5V, G2B'=GND, G2A'=IO/M'. Y2' enables ROM1 (4000H–5FFFH), Y3' enables ROM2 (6000H–7FFFH). RD' drives OE', A12–A0 connect to address lines, and data lines to D7–D0.

Design an address decoding circuit to interface two 8k*8 ROM chips at address starting at 4000H.

An 8K×8 ROM has 8192 = 2¹³ locations, so it needs 13 address lines (A12–A0). The remaining lines A15, A14, A13 are used for chip selection.

Address map

ChipA15 A14 A13Address range
ROM 10 1 04000H – 5FFFH
ROM 20 1 16000H – 7FFFH

Check: 4000H + 2000H (8K) = 6000H, and 6000H + 2000H = 8000H, so the two chips are consecutive.

Decoder connections (74LS138)

  • C, B, A = A15, A14, A13. Pattern 010 gives Y2' (ROM 1); 011 gives Y3' (ROM 2).
  • G1 = +5 V, G2B' = GND.
  • G2A' = IO/M', so the decoder works only in memory cycles (IO/M' = 0).
  • Y2' → CE' of ROM 1; Y3' → CE' of ROM 2.
  • A12–A0 go to the address pins of both ROMs; D7–D0 to both data outputs.
  • RD' goes to OE' of both ROMs (ROM has no write).
 A15 --- C \
 A14 --- B  | 74LS138      +-------+
 A13 --- A /  Y2' -------- |CE' R1 | 4000-5FFF
 IO/M' - G2A' Y3' ----+    |8Kx8   |
 GND --- G2B'         |    +-------+
 +5V --- G1           |    +-------+
                      +--- |CE' R2 | 6000-7FFF
                           |8Kx8   |
 A12-A0 --> A12-A0 of both +-------+
 RD' --> OE' of both,  D7-D0 <-- data out

The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low.

✓ Answer checked by Claude Opus 5.5 (high effort)

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