Interface two 4K x 8 ROM with 3:8 decoder

A 4K×8 ROM needs 12 address lines (A11–A0). I place ROM 1 at 0000H (the reset address, where the monitor program normally starts) and ROM 2 immediately after it.

Address map

Circuit (74LS138)

• Select inputs C, B, A = A14, A13, A12. Pattern 000 → Y0' (ROM 1); 001 → Y1' (ROM 2).
• A15 must be 0 for both ROMs: connect A15 to G2A'.
• IO/M' to G2B' (must be 0 for memory access). G1 = +5 V.
• Y0' → CE' of ROM 1; Y1' → CE' of ROM 2.
• A11–A0 go to both ROMs; RD' to OE' of both ROMs; D7–D0 from both ROMs to the data bus.

 A14 --- C \
 A13 --- B  | 74LS138       +-------+
 A12 --- A /   Y0' -------- |CE' R1 | 0000-0FFF
 A15 --- G2A'  Y1' ---+     +-------+
 IO/M' - G2B'         |     +-------+
 +5V --- G1           +-----|CE' R2 | 1000-1FFF
                            +-------+
 A11-A0 -> A11-A0 of both ROMs
 RD' -> OE' of both ROMs; D7-D0 <- ROM data

Explanation

• When the 8085 reads an address in 0000H–0FFFH, A15–A12 = 0000, so Y0' goes low and only ROM 1 is enabled. A11–A0 select the byte in the chip, and RD' makes the chip put it on the data bus.
• For 1000H–1FFFH, A15–A12 = 0001 and Y1' enables ROM 2.
• Outputs Y2'–Y7' (2000H–7FFFH) are unused and can be used for more memory later. A15 = 1 disables the decoder, so the upper half of memory is free.
• Only one ROM is enabled at a time, so there is no bus conflict.

The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low.