Interface circuit with 2 RAMs and 2 ROMs

Given: a processor with a 16-bit address bus (64 KB space) and an 8-bit data bus, and four chips of 8 KB each: ROM1, ROM2, RAM1, RAM2.

Address lines

8 KB = 2^13 bytes, so each chip needs 13 address lines (A12-A0), connected in parallel to all chips. The remaining lines A15, A14 and A13 are used for chip selection. With four chips (32 KB in total), A14 and A13 select one chip, and A15 enables the decoder (the memory occupies the lower 32 KB).

Chip-select logic

A 2-to-4 decoder (e.g. 74LS139) is used, with its active-low enable input G' driven by A15.

Circuit

              +-------------------------------+
 A12..A0 -----+--> A of ROM1, ROM2, RAM1, RAM2 |
              +-------------------------------+
 A15 ------> G' +-----------+
 A14 ------> B  | 2-to-4    |--Y0'--> CS' ROM1
 A13 ------> A  | decoder   |--Y1'--> CS' ROM2
                |           |--Y2'--> CS' RAM1
                +-----------+--Y3'--> CS' RAM2
 RD' -------> OE' of all four chips
 WR' -------> WE' of RAM1 and RAM2 only (ROMs are read-only)
 D7..D0 <===> data pins of every chip (tri-state, shared)

Operation: when the processor outputs an address, A15 = 0 enables the decoder, and A14A13 activates the chip select of exactly one chip. Only that chip drives the data bus (read) or latches it (RAM write), using A12-A0 for the location within the chip. RD' and WR' act as the read and write strobes. The ROMs hold the program (booting from 0000H) and the RAMs hold data and the stack.