How interrupts interface with microprocessor

A microprocessor has one or a few interrupt input pins (such as INTR, NMI), while a system has many devices that can interrupt. The devices are connected to the processor through an interrupt controller (e.g. the Intel 8259 PIC).

 Device 0 -- IRQ0 --+
 Device 1 -- IRQ1 --+--> +-------------+  INT   +-----------+
 Device 2 -- IRQ2 --+    | Interrupt   |------->|           |
   ...                   | controller  |  INTA  | Micro-    |
 Device 7 -- IRQ7 --+    | (priority,  |<-------| processor |
                         |  mask)      |  D0-D7 |           |
                         +------+------+<======>+-----------+
                                (vector on data bus)

Operation

1. A device raises its IRQ line. The controller checks the mask and priority and sends INT to the processor.
2. The processor finishes the current instruction, saves the PC and flags on the stack, and sends INTA.
3. The controller puts the interrupt vector number (or the call instruction with the ISR address) on the data bus.
4. The processor uses the vector to look up the IVT, loads the ISR address into the PC and runs the ISR.
5. At the end, a return-from-interrupt instruction (IRET/RETI) restores the PC and flags and the main program continues.

The interrupt controller thus provides many interrupt lines, priority resolution, masking and the vector, and so interfaces many devices with the single INT pin. Non-maskable interrupt (NMI) cannot be disabled and is used for critical events such as power failure.