- 2082 Baisakh · 5 marks
Circuit giving 2's complement of a 4-bit number
Short answer
Output Y0 = A0, Y1 = A1⊕A0, Y2 = A2⊕(A1+A0), Y3 = A3⊕(A2+A1+A0). Realized with three XOR and two OR gates. This implements the rule: copy bits from LSB up to and including the first 1, then invert all higher bits.
Design a combinational circuit whose input is 4-bit number and output is 2's complement of input number.
The circuit takes a 4-bit number and gives = its 2's complement (, keeping 4 bits).
Truth table
| 0000 | 0000 | 1000 | 1000 | |
| 0001 | 1111 | 1001 | 0111 | |
| 0010 | 1110 | 1010 | 0110 | |
| 0011 | 1101 | 1011 | 0101 | |
| 0100 | 1100 | 1100 | 0100 | |
| 0101 | 1011 | 1101 | 0011 | |
| 0110 | 1010 | 1110 | 0010 | |
| 0111 | 1001 | 1111 | 0001 |
Simplified expressions
From K-maps (or from the rule "copy bits up to and including the first 1 from the right, then invert the rest"):
- for odd numbers only:
- for 01, 10 in :
- equals when , else :
- equals when , else :
Circuit
A0 ------------------------------> Y0
A1, A0 ----------[XOR]-----------> Y1
A1, A0 --[OR]--> X1 = A1+A0
A2, X1 ----------[XOR]-----------> Y2
A2, X1 --[OR]--> X2 = A2+A1+A0
A3, X2 ----------[XOR]-----------> Y3
Gates: 3 XOR and 2 OR gates (the second OR adds to the first OR output).
Check: : , , , , so , and . Correct.
(Alternative: invert each bit with NOT gates and add 1 using a 4-bit parallel adder with .)
✓ Answer checked by Claude Opus 5.5 (high effort)
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