3-input TTL NAND; totem-pole output

A 3-input TTL NAND gate (7410) is the same as the standard TTL NAND circuit, but the input transistor Q1 has three emitters, one for each input A, B, C.

              +5 V
   +-----------+----------+
 R1 4k      R2 1.6k    R4 130
   |           |          |
   b           +-----+    c
A--e  Q1       |     +--b Q3
B--e     c--+  c          e
C--e        +--b Q2       |
               e         D1
               +-----+    +---- Y
               |     |    c
             R3 1k   +--b Q4
               |          e
   GND --------+----------+

Operation

• Any input LOW: that emitter junction of Q1 is forward biased and Q1's base is held at about 0.9 V. No current reaches Q2's base, so Q2 and Q4 are OFF. Q2's collector is high (through R2), so Q3 is ON and the output is HIGH (≈ 3.4 V, ≥ 2.4 V guaranteed).
• All inputs HIGH: all three emitter junctions are reverse biased. R1 current flows through Q1's base–collector junction into Q2, so Q2 and Q4 saturate and the output is LOW (≈ 0.2 V). Q2's collector is about 0.9 V, too low to turn on Q3 and D1, so Q3 is OFF.

So $Y = \overline{ABC}$.

Significance of the totem-pole output

• Q3 (pull-up) and Q4 (pull-down) are stacked; only one is ON at a time. Q3 actively sources current for a HIGH output, Q4 sinks current for a LOW output.
• Both states have low output resistance, so the load capacitance charges and discharges quickly: fast switching and good fan-out (10).
• Lower power than a resistor pull-up, since no resistor current flows in the LOW state.
• D1 keeps Q3 OFF when Q4 is ON; R4 (130 Ω) limits the current spike when both conduct for an instant during switching.
• Drawback: totem-pole outputs cannot be tied together (wired-AND), as a HIGH output shorted to a LOW one draws heavy current.