TTL NOR gate; totem pole

TTL NOR gate

A TTL NOR gate (7402) uses a separate input transistor and phase splitter for each input, with the phase splitters in parallel, followed by a totem-pole output.

                 +5 V
   +-------+--------+----------+
 R1A 4k  R1B 4k   R2 1.6k    R4 130
   |       |        |          |
   b       b        +-----+    c
A--e Q1A B-e Q1B    |     +--b Q3
   c       c        |          e
   |       |     +--+--+       |
   |       |     c     c      D1
   +-------)---b Q2A   |       |
           +---------b Q2B     |
                 e     e       +--- Y
                 +--+--+       c
                    |     +--b Q4
                    +-----+    e
                    |          |
                  R3 1k        |
   GND -------------+----------+

(")" marks a crossing without connection.)

Circuit (standard 7402):

• Each input has its own input transistor (Q1A for A, Q1B for B) and its own phase splitter (Q2A, Q2B).
• Q2A and Q2B are connected in parallel: collectors joined (to R2 and Q3 base), emitters joined (to R3 and Q4 base).
• The output stage is the usual totem pole Q3, D1, Q4.

Operation:

• A = 0, B = 0: both Q1A and Q1B conduct through their emitters, so their bases are near 0.9 V. Q2A and Q2B get no base current and are OFF, so Q4 is OFF and Q3 is ON → Y = 1 (HIGH).
• A = 1 (B any): Q1A's emitter junction is reverse biased; its base current flows through the base–collector junction into Q2A, which saturates. Q2A alone pulls the common collector line low (Q3 OFF) and drives Q4 ON → Y = 0.
• B = 1 (A any): the same happens through Q1B and Q2B → Y = 0.

Hence $Y = \overline{A + B}$: because the phase splitters are in parallel, either input HIGH is enough to pull the output LOW.

Totem pole

Totem-pole output is the TTL output stage in which two transistors are stacked one above the other between $V_{CC}$ and ground, like a totem pole: Q3 (active pull-up) on top with R4 = 130 Ω and diode D1, and Q4 (pull-down) below. The output Y is taken from their junction. The phase splitter Q2 drives them in opposite phase, so only one is ON at a time.

   +5 V
    |
  R4 130
    |
    c
Q2c-b Q3   (ON for HIGH output)
    e
    |
   D1
    +------- Y
    c
Q2e-b Q4   (ON for LOW output)
    e
    |
   GND

Significance:

• Low output resistance in both states: Q3 sources current and Q4 sinks current, so load capacitance is charged and discharged quickly → short rise and fall times, higher speed than a resistor pull-up.
• Low power: in the LOW state Q3 is OFF, so no current flows from $V_{CC}$ through a pull-up into the ON transistor, unlike a passive (resistor) pull-up.
• D1 adds an extra 0.7 V drop so that Q3 stays OFF when Q4 is saturated.
• R4 limits the current spike that flows for a few ns when both transistors are briefly ON during switching.
• Limitation: totem-pole outputs must not be wired together (wired-AND); if one output is HIGH and another LOW, a large current flows and may damage the gates. Open-collector or tristate outputs are used for bus connections.