How is the TTL NOR gate different from the TTL NAND gate in its internal structure?

It uses a separate input transistor and phase splitter per input, with the phase splitters in parallel

It uses a multi-emitter transistor with series output transistors

It uses phase splitters in series

Why is one HIGH input enough to make the output LOW?

Its phase splitter saturates and alone pulls the common collector line low (Q3 OFF) and drives Q4 ON

Its input transistor turns Q3 on

Both phase splitters must saturate

The HIGH input directly grounds the output

What logic function does the circuit realise and why?

Y = (A + B) complemented, because the parallel splitters make either HIGH input pull Y LOW

Y = AB complemented, because splitters are in series

Y = A + B, because it is non-inverting

2070 Chaitra · 6 marks

2-input TTL NOR gate

Short answer

In the 2-input TTL NOR gate, each input has its own transistor and phase splitter; the splitters are in parallel. If either input is high, that splitter saturates, pulling the common collector low, turning Q3 off and Q4 on, Y=0. Only when both inputs are low, both splitters off, Q3 on, Q4 off, Y=1, so Y = (A+B)'.

Draw the schematic diagram of TTL two input NOR Gate.

A TTL NOR gate (7402) uses a separate input transistor and phase splitter for each input, with the phase splitters in parallel, followed by a totem-pole output.

                 +5 V
   +-------+--------+----------+
 R1A 4k  R1B 4k   R2 1.6k    R4 130
   |       |        |          |
   b       b        +-----+    c
A--e Q1A B-e Q1B    |     +--b Q3
   c       c        |          e
   |       |     +--+--+       |
   |       |     c     c      D1
   +-------)---b Q2A   |       |
           +---------b Q2B     |
                 e     e       +--- Y
                 +--+--+       c
                    |     +--b Q4
                    +-----+    e
                    |          |
                  R3 1k        |
   GND -------------+----------+

(")" marks a crossing without connection.)

Circuit (standard 7402):

Each input has its own input transistor (Q1A for A, Q1B for B) and its own phase splitter (Q2A, Q2B).
Q2A and Q2B are connected in parallel: collectors joined (to R2 and Q3 base), emitters joined (to R3 and Q4 base).
The output stage is the usual totem pole Q3, D1, Q4.

Operation:

A = 0, B = 0: both Q1A and Q1B conduct through their emitters, so their bases are near 0.9 V. Q2A and Q2B get no base current and are OFF, so Q4 is OFF and Q3 is ON → Y = 1 (HIGH).
A = 1 (B any): Q1A's emitter junction is reverse biased; its base current flows through the base–collector junction into Q2A, which saturates. Q2A alone pulls the common collector line low (Q3 OFF) and drives Q4 ON → Y = 0.
B = 1 (A any): the same happens through Q1B and Q2B → Y = 0.

A	B	Q2A	Q2B	Q3	Q4	Y
0	0	OFF	OFF	ON	OFF	1
0	1	OFF	ON	OFF	ON	0
1	0	ON	OFF	OFF	ON	0
1	1	ON	ON	OFF	ON	0

Hence $Y = \overline{A + B}$ : because the phase splitters are in parallel, either input HIGH is enough to pull the output LOW.

✓ Answer checked by Claude Opus 5.5 (high effort)

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