How is the TTL OR gate (7432) built?

NOR input section followed by an extra inverting stage Q3 and a totem-pole output

NAND input section followed by a diode

Open-collector NOR with a pull-up

With A = B = 0, why is Y = 0?

Q2A and Q2B are OFF, node X rises and turns Q3 ON, which turns Q5 ON and Q4 OFF

Q2A and Q2B saturate and pull Y low

When A = 1 or B = 1, what happens?

A Q2 saturates, pulls X low, Q3 and Q5 turn OFF and Q4 turns ON, so Y = 1

Propagation delay of a gate is measured as the time between which points?

The 50% point of the input edge and the 50% point of the output edge

The 10% and 90% points of the output edge

The moment power is applied and the output becomes stable

The 0 V level of the input and the VCC level of the output

2076 Chaitra · 4+2 marks

TTL OR gate; propagation delay and power

Short answer

A TTL OR gate (7432) uses a NOR input stage with parallel phase splitters, then an inverter and totem-pole output, yielding Y = A+B. Propagation delay tpd is the average of low-to-high and high-to-low transition times measured at 50% points (~9–10 ns). Power dissipation is PD = VCC × ICC(avg), where ICC(avg) = (ICCH+ICCL)/2; typically 10 mW per gate.

Explain the operation of TTL two input OR gate with schematic diagram and also define the propagation delay time and power dissipation.

TTL two-input OR gate

A TTL OR gate (7432) is a NOR input section (two input transistors Q1A, Q1B with parallel stages Q2A, Q2B) followed by an extra inverting stage Q3 and a totem-pole output Q4–D1–Q5, so the output is the complement of NOR.

 Input section (NOR stage):
                 +5 V
   +-------+--------+
 R1A 4k  R1B 4k   R2 4k
   |       |        |
   b       b        +------- X
A--e Q1A B-e Q1B    |
   c       c     +--+--+
   |       |     c     c
   +-------)---b Q2A   |
           +---------b Q2B
                 e     e
                 +--+--+
                    |
                  R4 1k
                    |
                   GND

 Output section (common to AND and OR):
              +5 V
          +------+------+
       R3 1.6k       R5 130
          |             |
          +------+      c
          |      +----b Q4
          c             e
 X -----b Q3            |
          e            D1
          |             |
          +------+      +----- Y
          |      |      c
        R6 1k    +----b Q5
          |             e
 GND -----+-------------+

The joined collectors of Q2A and Q2B (node X) drive the base of Q3; the output section is the same as in a TTL AND gate.

Operation:

A = B = 0: Q1A and Q1B conduct through their emitters, so Q2A and Q2B are OFF. Node X rises through R2 and turns Q3 ON; Q3 turns Q5 ON and Q4 OFF → Y = 0.
A = 1 or B = 1: the corresponding Q2 saturates and pulls node X LOW → Q3 OFF → Q5 OFF, Q4 ON → Y = 1.

A	B	Q2A or Q2B ON?	Q3	Y
0	0	No	ON	0
0	1	Yes	OFF	1
1	0	Yes	OFF	1
1	1	Yes	OFF	1

So $Y = A + B$ .

Propagation delay time

The time between an input change and the resulting output change, measured at the 50% points: $t_{PHL}$ for a HIGH→LOW output and $t_{PLH}$ for LOW→HIGH; average $t_{pd} = (t_{PHL} + t_{PLH})/2$ (about 9–10 ns for standard TTL).

Power dissipation

The average power a gate takes from the supply:

P_D = V_{CC} \times I_{CC(avg)}, \qquad I_{CC(avg)} = \frac{I_{CCH} + I_{CCL}}{2}

For a 7400 package, $I_{CCH} = 4$ mA and $I_{CCL} = 12$ mA, so $I_{CC(avg)} = 8$ mA and $P_D = 5 \times 8 = 40$ mW per package, i.e. 10 mW per gate.

✓ Answer checked by Claude Opus 5.5 (high effort)

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