CMOS inverter / NOT gate operation

A CMOS inverter (NOT gate) is built from one p-channel enhancement MOSFET (PMOS) and one n-channel enhancement MOSFET (NMOS) connected in a complementary pair. Output is the logical complement of the input.

Structure

• The two gates are tied together and form the input Vin.
• The two drains are tied together and form the output Vout.
• The PMOS source is connected to VDD, the NMOS source is connected to ground.

        VDD
         |
     S --|  PMOS
 Vin o---| G
     D --|
         +-----o Vout
     D --|
 Vin o---| G   NMOS
     S --|
         |
        GND

Operation

• Vin = 0: VGS(NMOS) = 0 < VT, so the NMOS is OFF. For the PMOS, VGS = −VDD, so it turns ON and connects the output to VDD. Output is high.
• Vin = VDD: the NMOS is ON (VGS = VDD) and pulls the output to ground. The PMOS has VGS = 0 so it is OFF. Output is low.

In the steady state one transistor is always OFF, so there is no direct path from VDD to ground. Static current is almost zero.

Transfer characteristic

 Vout
 VDD |----.
     |     \
     |      \   (sharp transition
     |       \   near VDD/2)
   0 |        '------
     +----------------- Vin
     0    VDD/2   VDD

During switching, both transistors are briefly ON, and a small current flows (dynamic power). Power consumption: P = C VDD² f.

Advantages: very low static power, high noise margin (about 0.45 VDD), output swings fully from 0 to VDD, high packing density. It is the basis of modern digital ICs.