3-input CMOS gate

A 3-input CMOS gate uses three PMOS–NMOS pairs. The 3-input CMOS NAND gate is shown: three PMOS in parallel from $V_{DD}$ to the output and three NMOS in series from the output to ground; each input drives one PMOS and one NMOS.

     VDD          VDD          VDD
      |            |            |
A --o| P1   B --o| P2   C --o| P3
      |            |            |
      +------------+------------+
                   |
                   +-------------- Y = (ABC)'
                   |
            A --| N1
                   |
            B --| N2
                   |
            C --| N3
                   |
                  GND

Operation

• A PMOS conducts when its gate is 0; an NMOS conducts when its gate is 1.
• Any input 0: the PMOS of that input is ON and connects Y to $V_{DD}$; the NMOS of that input is OFF, breaking the series path to ground → Y = 1.
• All inputs 1: all PMOS are OFF; all three series NMOS are ON and connect Y to ground → Y = 0.

So $Y = \overline{ABC}$. The pull-up and pull-down networks are never ON together, so static power is almost zero.

3-input NOR: swapping the arrangement (PMOS in series, NMOS in parallel) gives $Y = \overline{A + B + C}$: Y = 1 only when all inputs are 0.