Why is CMOS static power almost zero?

One of the pull-up/pull-down networks is always OFF

It uses bipolar transistors in saturation

Its inputs are shorted to ground

How is a TTL AND gate (7408) built from the NAND?

NAND input stage followed by an extra inverting stage and then a totem-pole output

Open-collector NAND with pull-up resistor

With any input LOW in the AND gate, why is Y = 0?

Q2 is OFF, node X turns Q3 ON, which turns Q5 ON and Q4 OFF

With A = B = 1, why is Y = 1?

Q2 saturates, pulling X low, so Q3 and Q5 are OFF and Q4 is ON

Q1 conducts through its emitters

Why does a TTL AND gate have a slightly longer delay than a NAND?

It has an extra inverting stage

2078 Bhadra · 3+4 marks

CMOS characteristics; TTL 2-input AND

Short answer

CMOS features very low static power (nW), dynamic power CL·VDD²·f, a wide supply range (3–15 V for 4000B), high noise margin (~30% VDD), fan-out ~50, and is sensitive to static. A TTL 2-input AND gate has a NAND front-end (multi-emitter Q1 and phase splitter Q2) followed by an inverter (Q3) and totem-pole output; Y = A·B. When both inputs are high, Q2 conducts, turning Q3 off and giving Y=1; otherwise Q2 is off and Y=0.

Explain the characteristics of CMOS logic families. Draw the schematic diagram of TTL 2-input AND gate and explain with necessary diagrams.

Characteristics of CMOS logic families

CMOS (complementary MOS) logic uses a PMOS pull-up and an NMOS pull-down network in each gate. Its main characteristics:

Characteristic	CMOS (4000B / 74HC, 5 V)
Supply voltage	3–15 V (4000B), 2–6 V (74HC)
Static power	almost zero (nW per gate): one network is always OFF
Dynamic power	$P_D = C_L V_{DD}^2 f$ , grows with frequency
Noise margin	high, about 30% of $V_{DD}$ (≈ 1.4 V at 5 V)
Propagation delay	25–100 ns (4000B), 8–10 ns (74HC)
Fan-out	about 50 (inputs draw almost no current)
Input impedance	very high (≈ $10^{12}$ Ω)
Weakness	damaged by static charge; unused inputs must not float

TTL 2-input AND gate

A TTL AND gate (7408) is a NAND input stage followed by one more inverting stage and the totem-pole output, so the output is the complement of NAND.

 Input section (NAND stage):
             +5 V
   +----------+
 R1 4k      R2 4k
   |          |
   b          +------- X
A--e  Q1      |
B--e    c--+  c
           +--b Q2
              e
              |
            R4 1k
              |
             GND

 Output section (common to AND and OR):
              +5 V
          +------+------+
       R3 1.6k       R5 130
          |             |
          +------+      c
          |      +----b Q4
          c             e
 X -----b Q3            |
          e            D1
          |             |
          +------+      +----- Y
          |      |      c
        R6 1k    +----b Q5
          |             e
 GND -----+-------------+

Node X (collector of Q2) drives the base of Q3. Q1 = multi-emitter input, Q2 = NAND stage, Q3 = phase splitter, Q4–D1–Q5 = totem-pole output.

Operation:

Any input LOW: Q1's base is held at about 0.9 V, so Q2 is OFF. Node X is pulled up by R2 and supplies base current to Q3, so Q3 turns ON, which turns Q5 ON and Q4 OFF → Y = 0.
A = B = 1: Q1's base current goes into Q2, so Q2 saturates and pulls node X (Q3's base) LOW → Q3 OFF → Q5 OFF, Q4 ON → Y = 1.

A	B	Q2	Q3	Q5	Y
0	0	OFF	ON	ON	0
0	1	OFF	ON	ON	0
1	0	OFF	ON	ON	0
1	1	ON	OFF	OFF	1

So $Y = AB$ . Because of the extra stage, a TTL AND gate has a slightly longer delay than a TTL NAND.

✓ Answer checked by Claude Opus 5.5 (high effort)

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