In the TTL NOR gate, what causes the output to go LOW?

Either input HIGH, which saturates its phase splitter, turning Q4 ON and Q3 OFF

How is the fan-out of standard TTL calculated and what is it?

IOH/IIH = 0.4 mA / 40 uA = 10 from the LOW state

Which set matches standard 74XX values?

Delay about 10 ns, power about 10 mW per gate, speed-power product about 100 pJ

Delay about 100 ns, power about 1 mW

Delay about 1 ns, power about 100 mW

Delay about 10 us, power about 10 uW

What is true about unused or unconnected TTL inputs?

They act as HIGH, but should still be tied to VCC through a resistor

2068 Baisakh · 6 marks

TTL NOR gate; 74XX characteristics

Short answer

A TTL NOR gate uses multiple emitter inputs with phase splitters; any input HIGH saturates a phase splitter, turning on Q4 and off Q3, giving Y=0. Standard 74XX characteristics: VCC=5V±5%, VIH=2V, VIL=0.8V, VOH=2.4V, VOL=0.4V, noise margin 0.4V, fan-out 10, propagation delay ~10ns, power ~10mW.

Draw the schematic diagram of TTL NOR gate. Discuss the characteristics of TTL 74XX series gates.

TTL NOR gate

                 +5 V
   +-------+--------+----------+
 R1A 4k  R1B 4k   R2 1.6k    R4 130
   |       |        |          |
   b       b        +-----+    c
A--e Q1A B-e Q1B    |     +--b Q3
   c       c        |          e
   |       |     +--+--+       |
   |       |     c     c      D1
   +-------)---b Q2A   |       |
           +---------b Q2B     |
                 e     e       +--- Y
                 +--+--+       c
                    |     +--b Q4
                    +-----+    e
                    |          |
                  R3 1k        |
   GND -------------+----------+

(")" marks a crossing without connection.)

Either input HIGH saturates its phase splitter (Q2A or Q2B) → Q4 ON, Q3 OFF → Y = 0. Both inputs LOW → Q2A, Q2B OFF → Q3 ON → Y = 1. So $Y = \overline{A + B}$ .

Characteristics of standard TTL 74XX series

Parameter	Value
Supply voltage	5 V ± 5% (4.75–5.25 V)
$V_{IH(min)}$ / $V_{IL(max)}$	2.0 V / 0.8 V
$V_{OH(min)}$ / $V_{OL(max)}$	2.4 V / 0.4 V
Noise margin	0.4 V
Input currents	$I_{IH} = 40\ \mu$ A, $I_{IL} = -1.6$ mA
Output currents	$I_{OH} = -400\ \mu$ A, $I_{OL} = 16$ mA
Fan-out	$I_{OL}/I_{IL} = 16/1.6 = 10$
Propagation delay	≈ 9–10 ns
Power per gate	≈ 10 mW
Speed–power product	≈ 100 pJ
Temperature range	0 to 70 °C (54XX: −55 to 125 °C)

Other points: totem-pole output (fast, but outputs cannot be wired together), unconnected inputs act as HIGH (but should be tied to $V_{CC}$ through a resistor), and current spikes during switching need decoupling capacitors. Improved families (74LS, 74S, 74ALS, 74F) trade speed against power.

✓ Answer checked by Claude Opus 5.5 (high effort)

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