TTL NOR gate; propagation delay

TTL NOR gate

A TTL NOR gate (7402) uses a separate input transistor and phase splitter for each input, with the phase splitters in parallel, followed by a totem-pole output.

                 +5 V
   +-------+--------+----------+
 R1A 4k  R1B 4k   R2 1.6k    R4 130
   |       |        |          |
   b       b        +-----+    c
A--e Q1A B-e Q1B    |     +--b Q3
   c       c        |          e
   |       |     +--+--+       |
   |       |     c     c      D1
   +-------)---b Q2A   |       |
           +---------b Q2B     |
                 e     e       +--- Y
                 +--+--+       c
                    |     +--b Q4
                    +-----+    e
                    |          |
                  R3 1k        |
   GND -------------+----------+

(")" marks a crossing without connection.)

Circuit (standard 7402):

• Each input has its own input transistor (Q1A for A, Q1B for B) and its own phase splitter (Q2A, Q2B).
• Q2A and Q2B are connected in parallel: collectors joined (to R2 and Q3 base), emitters joined (to R3 and Q4 base).
• The output stage is the usual totem pole Q3, D1, Q4.

Operation:

• A = 0, B = 0: both Q1A and Q1B conduct through their emitters, so their bases are near 0.9 V. Q2A and Q2B get no base current and are OFF, so Q4 is OFF and Q3 is ON → Y = 1 (HIGH).
• A = 1 (B any): Q1A's emitter junction is reverse biased; its base current flows through the base–collector junction into Q2A, which saturates. Q2A alone pulls the common collector line low (Q3 OFF) and drives Q4 ON → Y = 0.
• B = 1 (A any): the same happens through Q1B and Q2B → Y = 0.

Hence $Y = \overline{A + B}$: because the phase splitters are in parallel, either input HIGH is enough to pull the output LOW.

Propagation delay

Propagation delay is the time between a change at a gate's input and the resulting change at its output, measured between the 50% points of the two edges. It has two values: $t_{PHL}$ (output falls) and $t_{PLH}$ (output rises); the average is $t_{pd} = (t_{PHL} + t_{PLH})/2$. For standard TTL (7400) $t_{pd} \approx 9$–10 ns. It sets the maximum speed of the gate.