Propagation delay; 3-input CMOS NOR

Propagation delay

Propagation delay is the time between a change at a gate's input and the resulting change at its output, measured between the 50% points of the input and output edges.

• $t_{PHL}$: delay when the output goes from HIGH to LOW.
• $t_{PLH}$: delay when the output goes from LOW to HIGH.
• Average delay: $t_{pd} = \dfrac{t_{PHL} + t_{PLH}}{2}$.

 In   ____/--------\______
          50%      50%
 Out  -------\________/----
          |<->|    |<->|
          tPHL     tPLH

It limits the maximum operating speed (typical: about 10 ns for 74LS TTL, about 8–10 ns for 74HC CMOS).

3-input CMOS NOR gate

It uses 3 PMOS transistors in series between $V_{DD}$ and the output (pull-up network) and 3 NMOS transistors in parallel between the output and ground (pull-down network). Each input A, B, C drives the gates of one PMOS and one NMOS.

          VDD
           |
    A --o| P1
           |
    B --o| P2
           |
    C --o| P3
           |
           +------------- Y = (A+B+C)'
           |       |       |
    A --| N1  B --| N2  C --| N3
           |       |       |
          GND     GND     GND

Operation:

• All inputs 0: all three PMOS are ON (gate low) and all NMOS are OFF. The series PMOS chain connects Y to $V_{DD}$, so Y = 1.
• Any input 1: that input's NMOS turns ON and pulls Y to ground, and its PMOS turns OFF, breaking the pull-up chain. So Y = 0.
• In every case only one network conducts, so no steady current flows from $V_{DD}$ to ground: static power is almost zero.

Hence $Y = \overline{A + B + C}$.