How does CMOS power dissipation behave?

Static power is almost zero, while dynamic power C_L V_DD^2 f rises with frequency

Static power is high and dynamic power is zero

Both are independent of frequency

Dynamic power is independent of supply voltage

Why is CMOS fan-out very high (about 50)?

MOS inputs draw almost no DC current

Outputs can supply very large currents

Propagation delay is very short

In a 2-input CMOS NOR gate, how are the transistors connected?

PMOS in series, NMOS in parallel

PMOS in parallel, NMOS in series

For A = 0 and B = 1 in the CMOS NOR gate, which is correct?

N2 is ON and P2 is OFF, so Y = 0

P1 and P2 are both ON, so Y = 1

N1 is ON and P1 is OFF, so Y = 0

What precaution is needed for CMOS gates?

Protect against static charge and never leave unused inputs floating

Always connect unused inputs to the output

Use a totem-pole output for each input

2081 Baisakh · 3+5 marks

CMOS characteristics; 2-input CMOS NOR

Short answer

CMOS gates feature near-zero static power, wide supply range (3-15V for 4000B), high noise margin (~30% VDD), and rail-to-rail output. A 2-input CMOS NOR uses series PMOS and parallel NMOS; output is high only when both inputs are low, otherwise low.

Explain the characteristics of CMOS gates and explain logic operation of CMOS 2-input NOR gate circuit with its truth table.

Characteristics of CMOS gates

CMOS (complementary MOS) gates use PMOS pull-up and NMOS pull-down transistors in pairs. Main characteristics (4000B and 74HC series):

Characteristic	Typical value / remark
Supply voltage	3–15 V (4000B), 2–6 V (74HC)
Logic levels (5 V CMOS, typical)	$V_{IL} \le 1.5$ V, $V_{IH} \ge 3.5$ V, $V_{OL} \approx 0.1$ V, $V_{OH} \approx 4.9$ V
Static power	almost zero (nW per gate)
Dynamic power	$P_D = C_L V_{DD}^2 f$ , rises with frequency
Noise margin	high, about 30% of $V_{DD}$ (1.4 V at 5 V)
Propagation delay	25–100 ns (4000B), about 8–10 ns (74HC)
Fan-out	very high (about 50) because MOS inputs draw almost no current
Handling	gate oxide is damaged by static charge; unused inputs must be tied to $V_{DD}$ or ground

2-input CMOS NOR gate

Two PMOS transistors $P_1$ , $P_2$ are in series from $V_{DD}$ to the output, and two NMOS transistors $N_1$ , $N_2$ are in parallel from the output to ground. Input A drives $P_1$ and $N_1$ ; input B drives $P_2$ and $N_2$ .

            VDD
             |
     A --o| P1
             |
     B --o| P2
             |
             +---------- Y = (A+B)'
             |        |
     A ---| N1  B ---| N2
             |        |
            GND      GND

A PMOS is ON when its gate is 0; an NMOS is ON when its gate is 1.

Operation:

A = 0, B = 0: $P_1$ , $P_2$ ON; $N_1$ , $N_2$ OFF. Output connected to $V_{DD}$ → Y = 1.
A = 0, B = 1: $N_2$ ON pulls output to ground; $P_2$ OFF breaks the pull-up path → Y = 0.
A = 1, B = 0: $N_1$ ON, $P_1$ OFF → Y = 0.
A = 1, B = 1: both NMOS ON, both PMOS OFF → Y = 0.

A	B	P1	P2	N1	N2	Y
0	0	ON	ON	OFF	OFF	1
0	1	ON	OFF	OFF	ON	0
1	0	OFF	ON	ON	OFF	0
1	1	OFF	OFF	ON	ON	0

So $Y = \overline{A + B}$ . Since the pull-up and pull-down networks are never ON together in steady state, no DC path exists from $V_{DD}$ to ground, which is why CMOS static power is so low.

✓ Answer checked by Claude Opus 5.5 (high effort)

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